8063396bf3
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/*
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* Allwinner H3 SDRAM Controller emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
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#define HW_MISC_ALLWINNER_H3_DRAMC_H
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#include "qom/object.h"
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#include "hw/sysbus.h"
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#include "exec/hwaddr.h"
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/**
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* Constants
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* @{
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*/
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/** Highest register address used by DRAMCOM module */
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#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
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/** Total number of known DRAMCOM registers */
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#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMCTL module */
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#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
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/** Total number of known DRAMCTL registers */
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#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMPHY module */
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#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
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/** Total number of known DRAMPHY registers */
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#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** @} */
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/**
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* Object model
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* @{
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*/
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#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
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OBJECT_DECLARE_SIMPLE_TYPE(AwH3DramCtlState, AW_H3_DRAMC)
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/** @} */
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/**
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* Allwinner H3 SDRAM Controller object instance state.
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*/
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struct AwH3DramCtlState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/** Physical base address for start of RAM */
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hwaddr ram_addr;
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/** Total RAM size in megabytes */
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uint32_t ram_size;
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/**
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* @name Memory Regions
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* @{
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*/
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MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
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MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
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MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
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MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
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MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
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/** @} */
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/**
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* @name Hardware Registers
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* @{
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*/
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uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
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uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
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uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
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/** @} */
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};
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#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
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