6bd039cdbe
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201019061126.3102-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
304 lines
8.5 KiB
C
304 lines
8.5 KiB
C
/*
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* Miscellaneous PowerPC emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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#include "helper_regs.h"
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/*****************************************************************************/
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/* SPR accesses */
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void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
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{
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qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
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env->spr[sprn]);
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}
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void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
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{
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qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
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env->spr[sprn]);
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}
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#ifdef TARGET_PPC64
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static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit,
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const char *caller, uint32_t cause,
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uintptr_t raddr)
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{
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qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n",
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bit, caller);
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env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
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raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr);
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}
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static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
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uint32_t sprn, uint32_t cause,
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uintptr_t raddr)
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{
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qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
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env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
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cause &= FSCR_IC_MASK;
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env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
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raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
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}
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#endif
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void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
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const char *caller, uint32_t cause)
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{
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#ifdef TARGET_PPC64
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if ((env->msr_mask & MSR_HVB) && !msr_hv &&
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!(env->spr[SPR_HFSCR] & (1UL << bit))) {
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raise_hv_fu_exception(env, bit, caller, cause, GETPC());
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}
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#endif
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}
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void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
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uint32_t sprn, uint32_t cause)
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{
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#ifdef TARGET_PPC64
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if (env->spr[SPR_FSCR] & (1ULL << bit)) {
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/* Facility is enabled, continue */
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return;
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}
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raise_fu_exception(env, bit, sprn, cause, GETPC());
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#endif
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}
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void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
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uint32_t sprn, uint32_t cause)
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{
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#ifdef TARGET_PPC64
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if (env->msr & (1ULL << bit)) {
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/* Facility is enabled, continue */
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return;
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}
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raise_fu_exception(env, bit, sprn, cause, GETPC());
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#endif
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}
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#if !defined(CONFIG_USER_ONLY)
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void helper_store_sdr1(CPUPPCState *env, target_ulong val)
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{
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if (env->spr[SPR_SDR1] != val) {
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ppc_store_sdr1(env, val);
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tlb_flush(env_cpu(env));
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}
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}
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#if defined(TARGET_PPC64)
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void helper_store_ptcr(CPUPPCState *env, target_ulong val)
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{
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if (env->spr[SPR_PTCR] != val) {
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ppc_store_ptcr(env, val);
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tlb_flush(env_cpu(env));
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}
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}
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void helper_store_pcr(CPUPPCState *env, target_ulong value)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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env->spr[SPR_PCR] = value & pcc->pcr_mask;
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}
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/*
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* DPDES register is shared. Each bit reflects the state of the
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* doorbell interrupt of a thread of the same core.
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*/
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target_ulong helper_load_dpdes(CPUPPCState *env)
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{
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target_ulong dpdes = 0;
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helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
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/* TODO: TCG supports only one thread */
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if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
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dpdes = 1;
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}
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return dpdes;
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}
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void helper_store_dpdes(CPUPPCState *env, target_ulong val)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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CPUState *cs = CPU(cpu);
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helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
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/* TODO: TCG supports only one thread */
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if (val & ~0x1) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
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TARGET_FMT_lx"\n", val);
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return;
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}
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if (val & 0x1) {
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env->pending_interrupts |= 1 << PPC_INTERRUPT_DOORBELL;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
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}
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}
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#endif /* defined(TARGET_PPC64) */
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void helper_store_pidr(CPUPPCState *env, target_ulong val)
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{
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env->spr[SPR_BOOKS_PID] = val;
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tlb_flush(env_cpu(env));
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}
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void helper_store_lpidr(CPUPPCState *env, target_ulong val)
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{
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env->spr[SPR_LPIDR] = val;
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/*
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* We need to flush the TLB on LPID changes as we only tag HV vs
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* guest in TCG TLB. Also the quadrants means the HV will
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* potentially access and cache entries for the current LPID as
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* well.
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*/
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tlb_flush(env_cpu(env));
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}
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void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
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{
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target_ulong hid0;
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hid0 = env->spr[SPR_HID0];
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if ((val ^ hid0) & 0x00000008) {
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/* Change current endianness */
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env->hflags &= ~(1 << MSR_LE);
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env->hflags_nmsr &= ~(1 << MSR_LE);
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env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
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env->hflags |= env->hflags_nmsr;
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qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
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val & 0x8 ? 'l' : 'b', env->hflags);
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}
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env->spr[SPR_HID0] = (uint32_t)val;
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}
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void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
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{
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if (likely(env->pb[num] != value)) {
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env->pb[num] = value;
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/* Should be optimized */
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tlb_flush(env_cpu(env));
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}
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}
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void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
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{
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store_40x_dbcr0(env, val);
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}
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void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
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{
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store_40x_sler(env, val);
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}
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#endif
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/*****************************************************************************/
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/* PowerPC 601 specific instructions (POWER bridge) */
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target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
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{
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switch (arg) {
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case 0x0CUL:
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/* Instruction cache line size */
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return env->icache_line_size;
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case 0x0DUL:
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/* Data cache line size */
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return env->dcache_line_size;
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case 0x0EUL:
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/* Minimum cache line size */
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return (env->icache_line_size < env->dcache_line_size) ?
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env->icache_line_size : env->dcache_line_size;
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case 0x0FUL:
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/* Maximum cache line size */
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return (env->icache_line_size > env->dcache_line_size) ?
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env->icache_line_size : env->dcache_line_size;
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default:
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/* Undefined */
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return 0;
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}
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}
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/*****************************************************************************/
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/* Special registers manipulation */
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/* GDBstub can read and write MSR... */
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void ppc_store_msr(CPUPPCState *env, target_ulong value)
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{
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hreg_store_msr(env, value, 0);
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}
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/*
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* This code is lifted from MacOnLinux. It is called whenever THRM1,2
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* or 3 is read an fixes up the values in such a way that will make
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* MacOS not hang. These registers exist on some 75x and 74xx
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* processors.
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*/
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void helper_fixup_thrm(CPUPPCState *env)
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{
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target_ulong v, t;
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int i;
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#define THRM1_TIN (1 << 31)
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#define THRM1_TIV (1 << 30)
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#define THRM1_THRES(x) (((x) & 0x7f) << 23)
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#define THRM1_TID (1 << 2)
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#define THRM1_TIE (1 << 1)
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#define THRM1_V (1 << 0)
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#define THRM3_E (1 << 0)
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if (!(env->spr[SPR_THRM3] & THRM3_E)) {
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return;
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}
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/* Note: Thermal interrupts are unimplemented */
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for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
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v = env->spr[i];
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if (!(v & THRM1_V)) {
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continue;
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}
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v |= THRM1_TIV;
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v &= ~THRM1_TIN;
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t = v & THRM1_THRES(127);
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if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
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v |= THRM1_TIN;
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}
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if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
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v |= THRM1_TIN;
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}
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env->spr[i] = v;
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}
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}
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