88c756bc9e
Currently the sbsa_gdwt watchdog device hardcodes its frequency at 62.5MHz. In real hardware, this watchdog is supposed to be driven from the system counter, which also drives the CPU generic timers. Newer CPU types (in particular from Armv8.6) should have a CPU generic timer frequency of 1GHz, so we can't leave the watchdog on the old QEMU default of 62.5GHz. Make the frequency a QOM property so it can be set by the board, and have our only board that uses this device set that frequency to the same value it sets the CPU frequency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
/*
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* Copyright (c) 2020 Linaro Limited
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*
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* Authors:
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* Shashi Mallela <shashi.mallela@linaro.org>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at your
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* option) any later version. See the COPYING file in the top-level directory.
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*
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*/
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#ifndef WDT_SBSA_GWDT_H
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#define WDT_SBSA_GWDT_H
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#include "qemu/bitops.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#define TYPE_WDT_SBSA "sbsa_gwdt"
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#define SBSA_GWDT(obj) \
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OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA)
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#define SBSA_GWDT_CLASS(klass) \
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OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA)
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#define SBSA_GWDT_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA)
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/* SBSA Generic Watchdog register definitions */
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/* refresh frame */
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#define SBSA_GWDT_WRR 0x000
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/* control frame */
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#define SBSA_GWDT_WCS 0x000
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#define SBSA_GWDT_WOR 0x008
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#define SBSA_GWDT_WORU 0x00C
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#define SBSA_GWDT_WCV 0x010
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#define SBSA_GWDT_WCVU 0x014
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/* Watchdog Interface Identification Register */
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#define SBSA_GWDT_W_IIDR 0xFCC
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/* Watchdog Control and Status Register Bits */
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#define SBSA_GWDT_WCS_EN BIT(0)
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#define SBSA_GWDT_WCS_WS0 BIT(1)
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#define SBSA_GWDT_WCS_WS1 BIT(2)
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#define SBSA_GWDT_WOR_MASK 0x0000FFFF
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/*
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* Watchdog Interface Identification Register definition
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* considering JEP106 code for ARM in Bits [11:0]
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*/
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#define SBSA_GWDT_ID 0x1043B
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/* 2 Separate memory regions for each of refresh & control register frames */
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#define SBSA_GWDT_RMMIO_SIZE 0x1000
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#define SBSA_GWDT_CMMIO_SIZE 0x1000
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typedef struct SBSA_GWDTState {
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/* <private> */
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion rmmio;
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MemoryRegion cmmio;
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qemu_irq irq;
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QEMUTimer *timer;
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uint64_t freq;
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uint32_t id;
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uint32_t wcs;
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uint32_t worl;
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uint32_t woru;
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uint32_t wcvl;
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uint32_t wcvu;
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} SBSA_GWDTState;
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#endif /* WDT_SBSA_GWDT_H */
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