8063396bf3
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/*
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* STM32F2XX ADC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_STM32F2XX_ADC_H
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#define HW_STM32F2XX_ADC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define ADC_SR 0x00
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#define ADC_CR1 0x04
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#define ADC_CR2 0x08
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#define ADC_SMPR1 0x0C
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#define ADC_SMPR2 0x10
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#define ADC_JOFR1 0x14
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#define ADC_JOFR2 0x18
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#define ADC_JOFR3 0x1C
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#define ADC_JOFR4 0x20
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#define ADC_HTR 0x24
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#define ADC_LTR 0x28
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#define ADC_SQR1 0x2C
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#define ADC_SQR2 0x30
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#define ADC_SQR3 0x34
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#define ADC_JSQR 0x38
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#define ADC_JDR1 0x3C
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#define ADC_JDR2 0x40
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#define ADC_JDR3 0x44
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#define ADC_JDR4 0x48
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#define ADC_DR 0x4C
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#define ADC_CR2_ADON 0x01
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#define ADC_CR2_CONT 0x02
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#define ADC_CR2_ALIGN 0x800
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#define ADC_CR2_SWSTART 0x40000000
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#define ADC_CR1_RES 0x3000000
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#define ADC_COMMON_ADDRESS 0x100
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#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
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OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXADCState, STM32F2XX_ADC)
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struct STM32F2XXADCState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint32_t adc_sr;
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uint32_t adc_cr1;
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uint32_t adc_cr2;
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uint32_t adc_smpr1;
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uint32_t adc_smpr2;
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uint32_t adc_jofr[4];
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uint32_t adc_htr;
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uint32_t adc_ltr;
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uint32_t adc_sqr1;
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uint32_t adc_sqr2;
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uint32_t adc_sqr3;
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uint32_t adc_jsqr;
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uint32_t adc_jdr[4];
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uint32_t adc_dr;
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qemu_irq irq;
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};
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#endif /* HW_STM32F2XX_ADC_H */
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