Matheus Ferst 6addef4d27 target/ppc: implement addg6s ... Implements the following Power ISA v2.06 instruction: addg6s: Add and Generate Sixes Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-10-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>		2022-07-06 10:22:38 -03:00
..
branch-impl.c.inc	PPC64/TCG: Implement 'rfebb' instruction	2021-12-17 17:57:19 +01:00
dfp-impl.c.inc	target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree	2021-11-09 10:32:52 +11:00
fixedpoint-impl.c.inc	target/ppc: implement addg6s	2022-07-06 10:22:38 -03:00
fp-impl.c.inc	target/ppc: Implement mffscdrn[i] instructions	2022-07-06 10:22:38 -03:00
fp-ops.c.inc	target/ppc: Move mffs[.] to decodetree	2022-07-06 10:22:38 -03:00
spe-impl.c.inc	ppc patch queue 2020-08-18	2020-08-24 09:35:21 +01:00
spe-ops.c.inc	meson: rename included C source files to .c.inc	2020-08-21 06:18:30 -04:00
vmx-impl.c.inc	target/ppc: use int128.h methods in vsubcuq	2022-07-06 10:22:38 -03:00
vmx-ops.c.inc	target/ppc: use int128.h methods in vsubcuq	2022-07-06 10:22:38 -03:00
vsx-impl.c.inc	target/ppc: Implemented [pm]xvbf16ger2*	2022-05-26 17:11:33 -03:00
vsx-ops.c.inc	target/ppc: declare xxextractuw and xxinsertw helpers with call flags	2022-05-26 17:11:32 -03:00