721 lines
19 KiB
C
721 lines
19 KiB
C
/*
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* SMSC 91C111 Ethernet interface emulation
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*
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* Copyright (c) 2005 CodeSourcery, LLC.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL
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*/
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#include "hw.h"
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#include "net.h"
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#include "devices.h"
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/* For crc32 */
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#include <zlib.h>
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/* Number of 2k memory pages available. */
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#define NUM_PACKETS 4
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typedef struct {
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VLANClientState *vc;
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uint16_t tcr;
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uint16_t rcr;
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uint16_t cr;
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uint16_t ctr;
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uint16_t gpr;
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uint16_t ptr;
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uint16_t ercv;
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qemu_irq irq;
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int bank;
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int packet_num;
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int tx_alloc;
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/* Bitmask of allocated packets. */
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int allocated;
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int tx_fifo_len;
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int tx_fifo[NUM_PACKETS];
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int rx_fifo_len;
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int rx_fifo[NUM_PACKETS];
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int tx_fifo_done_len;
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int tx_fifo_done[NUM_PACKETS];
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/* Packet buffer memory. */
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uint8_t data[NUM_PACKETS][2048];
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uint8_t int_level;
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uint8_t int_mask;
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uint8_t macaddr[6];
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int mmio_index;
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} smc91c111_state;
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#define RCR_SOFT_RST 0x8000
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#define RCR_STRIP_CRC 0x0200
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#define RCR_RXEN 0x0100
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#define TCR_EPH_LOOP 0x2000
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#define TCR_NOCRC 0x0100
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#define TCR_PAD_EN 0x0080
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#define TCR_FORCOL 0x0004
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#define TCR_LOOP 0x0002
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#define TCR_TXEN 0x0001
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#define INT_MD 0x80
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#define INT_ERCV 0x40
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#define INT_EPH 0x20
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#define INT_RX_OVRN 0x10
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#define INT_ALLOC 0x08
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#define INT_TX_EMPTY 0x04
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#define INT_TX 0x02
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#define INT_RCV 0x01
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#define CTR_AUTO_RELEASE 0x0800
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#define CTR_RELOAD 0x0002
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#define CTR_STORE 0x0001
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#define RS_ALGNERR 0x8000
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#define RS_BRODCAST 0x4000
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#define RS_BADCRC 0x2000
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#define RS_ODDFRAME 0x1000
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#define RS_TOOLONG 0x0800
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#define RS_TOOSHORT 0x0400
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#define RS_MULTICAST 0x0001
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/* Update interrupt status. */
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static void smc91c111_update(smc91c111_state *s)
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{
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int level;
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if (s->tx_fifo_len == 0)
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s->int_level |= INT_TX_EMPTY;
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if (s->tx_fifo_done_len != 0)
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s->int_level |= INT_TX;
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level = (s->int_level & s->int_mask) != 0;
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qemu_set_irq(s->irq, level);
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}
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/* Try to allocate a packet. Returns 0x80 on failure. */
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static int smc91c111_allocate_packet(smc91c111_state *s)
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{
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int i;
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if (s->allocated == (1 << NUM_PACKETS) - 1) {
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return 0x80;
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}
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for (i = 0; i < NUM_PACKETS; i++) {
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if ((s->allocated & (1 << i)) == 0)
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break;
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}
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s->allocated |= 1 << i;
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return i;
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}
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/* Process a pending TX allocate. */
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static void smc91c111_tx_alloc(smc91c111_state *s)
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{
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s->tx_alloc = smc91c111_allocate_packet(s);
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if (s->tx_alloc == 0x80)
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return;
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s->int_level |= INT_ALLOC;
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smc91c111_update(s);
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}
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/* Remove and item from the RX FIFO. */
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static void smc91c111_pop_rx_fifo(smc91c111_state *s)
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{
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int i;
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s->rx_fifo_len--;
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if (s->rx_fifo_len) {
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for (i = 0; i < s->rx_fifo_len; i++)
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s->rx_fifo[i] = s->rx_fifo[i + 1];
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s->int_level |= INT_RCV;
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} else {
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s->int_level &= ~INT_RCV;
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}
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smc91c111_update(s);
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}
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/* Remove an item from the TX completion FIFO. */
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static void smc91c111_pop_tx_fifo_done(smc91c111_state *s)
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{
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int i;
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if (s->tx_fifo_done_len == 0)
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return;
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s->tx_fifo_done_len--;
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for (i = 0; i < s->tx_fifo_done_len; i++)
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s->tx_fifo_done[i] = s->tx_fifo_done[i + 1];
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}
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/* Release the memory allocated to a packet. */
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static void smc91c111_release_packet(smc91c111_state *s, int packet)
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{
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s->allocated &= ~(1 << packet);
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if (s->tx_alloc == 0x80)
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smc91c111_tx_alloc(s);
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}
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/* Flush the TX FIFO. */
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static void smc91c111_do_tx(smc91c111_state *s)
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{
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int i;
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int len;
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int control;
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int add_crc;
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int packetnum;
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uint8_t *p;
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if ((s->tcr & TCR_TXEN) == 0)
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return;
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if (s->tx_fifo_len == 0)
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return;
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for (i = 0; i < s->tx_fifo_len; i++) {
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packetnum = s->tx_fifo[i];
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p = &s->data[packetnum][0];
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/* Set status word. */
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*(p++) = 0x01;
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*(p++) = 0x40;
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len = *(p++);
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len |= ((int)*(p++)) << 8;
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len -= 6;
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control = p[len + 1];
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if (control & 0x20)
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len++;
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/* ??? This overwrites the data following the buffer.
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Don't know what real hardware does. */
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if (len < 64 && (s->tcr & TCR_PAD_EN)) {
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memset(p + len, 0, 64 - len);
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len = 64;
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}
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#if 0
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/* The card is supposed to append the CRC to the frame. However
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none of the other network traffic has the CRC appended.
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Suspect this is low level ethernet detail we don't need to worry
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about. */
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add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
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if (add_crc) {
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uint32_t crc;
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crc = crc32(~0, p, len);
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memcpy(p + len, &crc, 4);
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len += 4;
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}
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#else
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add_crc = 0;
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#endif
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if (s->ctr & CTR_AUTO_RELEASE)
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/* Race? */
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smc91c111_release_packet(s, packetnum);
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else if (s->tx_fifo_done_len < NUM_PACKETS)
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s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum;
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qemu_send_packet(s->vc, p, len);
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}
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s->tx_fifo_len = 0;
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smc91c111_update(s);
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}
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/* Add a packet to the TX FIFO. */
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static void smc91c111_queue_tx(smc91c111_state *s, int packet)
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{
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if (s->tx_fifo_len == NUM_PACKETS)
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return;
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s->tx_fifo[s->tx_fifo_len++] = packet;
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smc91c111_do_tx(s);
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}
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static void smc91c111_reset(smc91c111_state *s)
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{
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s->bank = 0;
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s->tx_fifo_len = 0;
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s->tx_fifo_done_len = 0;
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s->rx_fifo_len = 0;
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s->allocated = 0;
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s->packet_num = 0;
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s->tx_alloc = 0;
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s->tcr = 0;
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s->rcr = 0;
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s->cr = 0xa0b1;
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s->ctr = 0x1210;
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s->ptr = 0;
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s->ercv = 0x1f;
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s->int_level = INT_TX_EMPTY;
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s->int_mask = 0;
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smc91c111_update(s);
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}
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#define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
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#define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
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static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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smc91c111_state *s = (smc91c111_state *)opaque;
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if (offset == 14) {
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s->bank = value;
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return;
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}
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if (offset == 15)
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return;
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switch (s->bank) {
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case 0:
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switch (offset) {
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case 0: /* TCR */
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SET_LOW(tcr, value);
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return;
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case 1:
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SET_HIGH(tcr, value);
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return;
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case 4: /* RCR */
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SET_LOW(rcr, value);
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return;
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case 5:
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SET_HIGH(rcr, value);
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if (s->rcr & RCR_SOFT_RST)
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smc91c111_reset(s);
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return;
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case 10: case 11: /* RPCR */
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/* Ignored */
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return;
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}
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break;
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case 1:
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switch (offset) {
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case 0: /* CONFIG */
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SET_LOW(cr, value);
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return;
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case 1:
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SET_HIGH(cr,value);
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return;
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case 2: case 3: /* BASE */
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case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
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/* Not implemented. */
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return;
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case 10: /* Genral Purpose */
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SET_LOW(gpr, value);
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return;
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case 11:
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SET_HIGH(gpr, value);
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return;
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case 12: /* Control */
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if (value & 1)
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fprintf(stderr, "smc91c111:EEPROM store not implemented\n");
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if (value & 2)
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fprintf(stderr, "smc91c111:EEPROM reload not implemented\n");
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value &= ~3;
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SET_LOW(ctr, value);
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return;
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case 13:
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SET_HIGH(ctr, value);
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return;
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}
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break;
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case 2:
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switch (offset) {
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case 0: /* MMU Command */
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switch (value >> 5) {
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case 0: /* no-op */
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break;
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case 1: /* Allocate for TX. */
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s->tx_alloc = 0x80;
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s->int_level &= ~INT_ALLOC;
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smc91c111_update(s);
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smc91c111_tx_alloc(s);
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break;
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case 2: /* Reset MMU. */
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s->allocated = 0;
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s->tx_fifo_len = 0;
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s->tx_fifo_done_len = 0;
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s->rx_fifo_len = 0;
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s->tx_alloc = 0;
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break;
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case 3: /* Remove from RX FIFO. */
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smc91c111_pop_rx_fifo(s);
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break;
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case 4: /* Remove from RX FIFO and release. */
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if (s->rx_fifo_len > 0) {
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smc91c111_release_packet(s, s->rx_fifo[0]);
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}
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smc91c111_pop_rx_fifo(s);
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break;
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case 5: /* Release. */
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smc91c111_release_packet(s, s->packet_num);
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break;
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case 6: /* Add to TX FIFO. */
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smc91c111_queue_tx(s, s->packet_num);
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break;
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case 7: /* Reset TX FIFO. */
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s->tx_fifo_len = 0;
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s->tx_fifo_done_len = 0;
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break;
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}
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return;
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case 1:
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/* Ignore. */
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return;
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case 2: /* Packet Number Register */
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s->packet_num = value;
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return;
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case 3: case 4: case 5:
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/* Should be readonly, but linux writes to them anyway. Ignore. */
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return;
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case 6: /* Pointer */
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SET_LOW(ptr, value);
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return;
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case 7:
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SET_HIGH(ptr, value);
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return;
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case 8: case 9: case 10: case 11: /* Data */
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{
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int p;
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int n;
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if (s->ptr & 0x8000)
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n = s->rx_fifo[0];
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else
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n = s->packet_num;
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p = s->ptr & 0x07ff;
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if (s->ptr & 0x4000) {
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s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff);
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} else {
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p += (offset & 3);
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}
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s->data[n][p] = value;
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}
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return;
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case 12: /* Interrupt ACK. */
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s->int_level &= ~(value & 0xd6);
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if (value & INT_TX)
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smc91c111_pop_tx_fifo_done(s);
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smc91c111_update(s);
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return;
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case 13: /* Interrupt mask. */
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s->int_mask = value;
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smc91c111_update(s);
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return;
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}
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break;;
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case 3:
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switch (offset) {
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case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
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/* Multicast table. */
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/* Not implemented. */
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return;
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case 8: case 9: /* Management Interface. */
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/* Not implemented. */
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return;
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case 12: /* Early receive. */
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s->ercv = value & 0x1f;
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case 13:
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/* Ignore. */
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return;
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}
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break;
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}
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hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
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}
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static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
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{
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smc91c111_state *s = (smc91c111_state *)opaque;
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if (offset == 14) {
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return s->bank;
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}
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if (offset == 15)
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return 0x33;
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switch (s->bank) {
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case 0:
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switch (offset) {
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case 0: /* TCR */
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return s->tcr & 0xff;
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case 1:
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return s->tcr >> 8;
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case 2: /* EPH Status */
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return 0;
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case 3:
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return 0x40;
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case 4: /* RCR */
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return s->rcr & 0xff;
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case 5:
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return s->rcr >> 8;
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case 6: /* Counter */
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case 7:
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/* Not implemented. */
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return 0;
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case 8: /* Memory size. */
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return NUM_PACKETS;
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case 9: /* Free memory available. */
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{
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int i;
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int n;
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n = 0;
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for (i = 0; i < NUM_PACKETS; i++) {
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if (s->allocated & (1 << i))
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n++;
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}
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return n;
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}
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case 10: case 11: /* RPCR */
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/* Not implemented. */
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return 0;
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}
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break;
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case 1:
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switch (offset) {
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case 0: /* CONFIG */
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return s->cr & 0xff;
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case 1:
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return s->cr >> 8;
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case 2: case 3: /* BASE */
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/* Not implemented. */
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return 0;
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case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
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return s->macaddr[offset - 4];
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case 10: /* General Purpose */
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return s->gpr & 0xff;
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case 11:
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return s->gpr >> 8;
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case 12: /* Control */
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return s->ctr & 0xff;
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case 13:
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return s->ctr >> 8;
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}
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break;
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case 2:
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switch (offset) {
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case 0: case 1: /* MMUCR Busy bit. */
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return 0;
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case 2: /* Packet Number. */
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return s->packet_num;
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case 3: /* Allocation Result. */
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return s->tx_alloc;
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case 4: /* TX FIFO */
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if (s->tx_fifo_done_len == 0)
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return 0x80;
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else
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return s->tx_fifo_done[0];
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case 5: /* RX FIFO */
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if (s->rx_fifo_len == 0)
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return 0x80;
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else
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return s->rx_fifo[0];
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case 6: /* Pointer */
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return s->ptr & 0xff;
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case 7:
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return (s->ptr >> 8) & 0xf7;
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case 8: case 9: case 10: case 11: /* Data */
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{
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int p;
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int n;
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if (s->ptr & 0x8000)
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n = s->rx_fifo[0];
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else
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n = s->packet_num;
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p = s->ptr & 0x07ff;
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if (s->ptr & 0x4000) {
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s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff);
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} else {
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p += (offset & 3);
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}
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return s->data[n][p];
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}
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case 12: /* Interrupt status. */
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return s->int_level;
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case 13: /* Interrupt mask. */
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return s->int_mask;
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}
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break;
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case 3:
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switch (offset) {
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case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
|
|
/* Multicast table. */
|
|
/* Not implemented. */
|
|
return 0;
|
|
case 8: /* Management Interface. */
|
|
/* Not implemented. */
|
|
return 0x30;
|
|
case 9:
|
|
return 0x33;
|
|
case 10: /* Revision. */
|
|
return 0x91;
|
|
case 11:
|
|
return 0x33;
|
|
case 12:
|
|
return s->ercv;
|
|
case 13:
|
|
return 0;
|
|
}
|
|
break;
|
|
}
|
|
hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset);
|
|
return 0;
|
|
}
|
|
|
|
static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
|
|
uint32_t value)
|
|
{
|
|
smc91c111_writeb(opaque, offset, value & 0xff);
|
|
smc91c111_writeb(opaque, offset + 1, value >> 8);
|
|
}
|
|
|
|
static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
|
|
uint32_t value)
|
|
{
|
|
/* 32-bit writes to offset 0xc only actually write to the bank select
|
|
register (offset 0xe) */
|
|
if (offset != 0xc)
|
|
smc91c111_writew(opaque, offset, value & 0xffff);
|
|
smc91c111_writew(opaque, offset + 2, value >> 16);
|
|
}
|
|
|
|
static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
|
|
{
|
|
uint32_t val;
|
|
val = smc91c111_readb(opaque, offset);
|
|
val |= smc91c111_readb(opaque, offset + 1) << 8;
|
|
return val;
|
|
}
|
|
|
|
static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
|
|
{
|
|
uint32_t val;
|
|
val = smc91c111_readw(opaque, offset);
|
|
val |= smc91c111_readw(opaque, offset + 2) << 16;
|
|
return val;
|
|
}
|
|
|
|
static int smc91c111_can_receive(void *opaque)
|
|
{
|
|
smc91c111_state *s = (smc91c111_state *)opaque;
|
|
|
|
if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
|
|
return 1;
|
|
if (s->allocated == (1 << NUM_PACKETS) - 1)
|
|
return 0;
|
|
return 1;
|
|
}
|
|
|
|
static void smc91c111_receive(void *opaque, const uint8_t *buf, int size)
|
|
{
|
|
smc91c111_state *s = (smc91c111_state *)opaque;
|
|
int status;
|
|
int packetsize;
|
|
uint32_t crc;
|
|
int packetnum;
|
|
uint8_t *p;
|
|
|
|
if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
|
|
return;
|
|
/* Short packets are padded with zeros. Receiving a packet
|
|
< 64 bytes long is considered an error condition. */
|
|
if (size < 64)
|
|
packetsize = 64;
|
|
else
|
|
packetsize = (size & ~1);
|
|
packetsize += 6;
|
|
crc = (s->rcr & RCR_STRIP_CRC) == 0;
|
|
if (crc)
|
|
packetsize += 4;
|
|
/* TODO: Flag overrun and receive errors. */
|
|
if (packetsize > 2048)
|
|
return;
|
|
packetnum = smc91c111_allocate_packet(s);
|
|
if (packetnum == 0x80)
|
|
return;
|
|
s->rx_fifo[s->rx_fifo_len++] = packetnum;
|
|
|
|
p = &s->data[packetnum][0];
|
|
/* ??? Multicast packets? */
|
|
status = 0;
|
|
if (size > 1518)
|
|
status |= RS_TOOLONG;
|
|
if (size & 1)
|
|
status |= RS_ODDFRAME;
|
|
*(p++) = status & 0xff;
|
|
*(p++) = status >> 8;
|
|
*(p++) = packetsize & 0xff;
|
|
*(p++) = packetsize >> 8;
|
|
memcpy(p, buf, size & ~1);
|
|
p += (size & ~1);
|
|
/* Pad short packets. */
|
|
if (size < 64) {
|
|
int pad;
|
|
|
|
if (size & 1)
|
|
*(p++) = buf[size - 1];
|
|
pad = 64 - size;
|
|
memset(p, 0, pad);
|
|
p += pad;
|
|
size = 64;
|
|
}
|
|
/* It's not clear if the CRC should go before or after the last byte in
|
|
odd sized packets. Linux disables the CRC, so that's no help.
|
|
The pictures in the documentation show the CRC aligned on a 16-bit
|
|
boundary before the last odd byte, so that's what we do. */
|
|
if (crc) {
|
|
crc = crc32(~0, buf, size);
|
|
*(p++) = crc & 0xff; crc >>= 8;
|
|
*(p++) = crc & 0xff; crc >>= 8;
|
|
*(p++) = crc & 0xff; crc >>= 8;
|
|
*(p++) = crc & 0xff; crc >>= 8;
|
|
}
|
|
if (size & 1) {
|
|
*(p++) = buf[size - 1];
|
|
*(p++) = 0x60;
|
|
} else {
|
|
*(p++) = 0;
|
|
*(p++) = 0x40;
|
|
}
|
|
/* TODO: Raise early RX interrupt? */
|
|
s->int_level |= INT_RCV;
|
|
smc91c111_update(s);
|
|
}
|
|
|
|
static CPUReadMemoryFunc *smc91c111_readfn[] = {
|
|
smc91c111_readb,
|
|
smc91c111_readw,
|
|
smc91c111_readl
|
|
};
|
|
|
|
static CPUWriteMemoryFunc *smc91c111_writefn[] = {
|
|
smc91c111_writeb,
|
|
smc91c111_writew,
|
|
smc91c111_writel
|
|
};
|
|
|
|
static void smc91c111_cleanup(VLANClientState *vc)
|
|
{
|
|
smc91c111_state *s = vc->opaque;
|
|
|
|
cpu_unregister_io_memory(s->mmio_index);
|
|
qemu_free(s);
|
|
}
|
|
|
|
void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
|
|
{
|
|
smc91c111_state *s;
|
|
|
|
qemu_check_nic_model(nd, "smc91c111");
|
|
|
|
s = (smc91c111_state *)qemu_mallocz(sizeof(smc91c111_state));
|
|
s->mmio_index = cpu_register_io_memory(0, smc91c111_readfn,
|
|
smc91c111_writefn, s);
|
|
cpu_register_physical_memory(base, 16, s->mmio_index);
|
|
s->irq = irq;
|
|
memcpy(s->macaddr, nd->macaddr, 6);
|
|
|
|
smc91c111_reset(s);
|
|
|
|
s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
|
|
smc91c111_receive, smc91c111_can_receive,
|
|
smc91c111_cleanup, s);
|
|
qemu_format_nic_info_str(s->vc, s->macaddr);
|
|
/* ??? Save/restore. */
|
|
}
|