Frank Chang 3a7f7757ba fpu/softfloat: set invalid excp flag for RISC-V muladd instructions ... In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled. In RISC-V Unprivileged ISA spec: The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are Inf and zero, even when the addend is a quiet NaN. This commit set invalid operation execption flag for RISC-V when multiplicands of muladd instructions are Inf and zero. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210420013150.21992-1-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-05-11 20:02:07 +10:00
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softfloat-specialize.c.inc	fpu/softfloat: set invalid excp flag for RISC-V muladd instructions	2021-05-11 20:02:07 +10:00
softfloat.c	softfloat: Define convert operations for bfloat16	2020-08-28 10:48:07 -07:00