Peter Maydell e1be0a576b nvic: Implement NVIC_ITNS<n> registers ... For v8M, the NVIC has a new set of registers per interrupt, NVIC_ITNS<n>. These determine whether the interrupt targets Secure or Non-secure state. Implement the register read/write code for these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER, NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure accesses to fields corresponding to interrupts which are configured to target secure state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org		2017-09-21 16:29:27 +01:00
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allwinner-a10-pic.h	Clean up header guards that don't match their file name	2016-07-12 16:19:16 +02:00
arm_gic_common.h	hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ	2017-01-20 11:15:09 +00:00
arm_gic.h	gic: provide defines for v2/v3 targetlist sizes	2016-07-14 16:51:37 +01:00
arm_gicv3_common.h	hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate	2017-02-28 17:10:00 +00:00
arm_gicv3_its_common.h	hw/intc/arm_gicv3_its: Implement state save/restore	2017-06-13 14:57:00 +01:00
arm_gicv3.h	hw/intc/arm_gicv3: ARM GICv3 device framework	2016-06-17 15:23:51 +01:00
armv7m_nvic.h	nvic: Implement NVIC_ITNS<n> registers	2017-09-21 16:29:27 +01:00
aspeed_vic.h	hw/intc: Add (new) ASPEED VIC device model	2016-03-16 17:42:18 +00:00
bcm2835_ic.h	bcm2835_ic: add bcm2835 interrupt controller	2016-02-03 15:00:44 +00:00
bcm2836_control.h	bcm2836_control: add bcm2836 ARM control logic	2016-02-03 15:00:45 +00:00
imx_avic.h	i.MX: Split AVIC emulator in a header file and a source file	2015-08-13 11:26:19 +01:00
intc.h	intc: add an interface to gather statistics/informations on interrupt controllers	2016-10-04 10:00:25 +02:00
mips_gic.h	Clean up ill-advised or unusual header guards	2016-07-12 16:20:46 +02:00
realview_gic.h