f22e598a72
Add support for optionally creating a PCIe/GPEX controller. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
/*
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* QEMU Xen PVH machine - common code.
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*
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* Copyright (c) 2024 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef XEN_PVH_COMMON_H__
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#define XEN_PVH_COMMON_H__
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#include <assert.h>
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#include "hw/sysbus.h"
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#include "hw/hw.h"
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#include "hw/xen/xen-hvm-common.h"
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#include "hw/pci-host/gpex.h"
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#define TYPE_XEN_PVH_MACHINE MACHINE_TYPE_NAME("xen-pvh-base")
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OBJECT_DECLARE_TYPE(XenPVHMachineState, XenPVHMachineClass,
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XEN_PVH_MACHINE)
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struct XenPVHMachineClass {
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MachineClass parent;
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/* PVH implementation specific init. */
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void (*init)(MachineState *state);
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/*
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* set_pci_intx_irq - Deliver INTX irqs to the guest.
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*
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* @opaque: pointer to XenPVHMachineState.
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* @irq: IRQ after swizzling, between 0-3.
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* @level: IRQ level.
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*/
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void (*set_pci_intx_irq)(void *opaque, int irq, int level);
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/*
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* set_pci_link_route: - optional implementation call to setup
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* routing between INTX IRQ (0 - 3) and GSI's.
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*
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* @line: line the INTx line (0 => A .. 3 => B)
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* @irq: GSI
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*/
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int (*set_pci_link_route)(uint8_t line, uint8_t irq);
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/*
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* Each implementation can optionally enable features that it
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* supports and are known to work.
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*/
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bool has_pci;
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bool has_tpm;
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bool has_virtio_mmio;
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};
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struct XenPVHMachineState {
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/*< private >*/
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MachineState parent;
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XenIOState ioreq;
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struct {
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MemoryRegion low;
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MemoryRegion high;
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} ram;
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struct {
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GPEXHost gpex;
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MemoryRegion mmio_alias;
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MemoryRegion mmio_high_alias;
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} pci;
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struct {
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MemMapEntry ram_low, ram_high;
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MemMapEntry tpm;
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/* Virtio-mmio */
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MemMapEntry virtio_mmio;
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uint32_t virtio_mmio_num;
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uint32_t virtio_mmio_irq_base;
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/* PCI */
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MemMapEntry pci_ecam, pci_mmio, pci_mmio_high;
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uint32_t pci_intx_irq_base;
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} cfg;
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};
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void xen_pvh_class_setup_common_props(XenPVHMachineClass *xpc);
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#endif
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