Joel Sing c13b169f1a

RISC-V: Clear load reservations on context switch and SC ...

This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.

Signed-off-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-06-25 22:37:04 -07:00

..

trans_privileged.inc.c

target/riscv: Add the privledge spec version 1.11.0

2019-06-24 01:03:45 -07:00

trans_rva.inc.c

RISC-V: Clear load reservations on context switch and SC

2019-06-25 22:37:04 -07:00

trans_rvd.inc.c

…

trans_rvf.inc.c

…

trans_rvi.inc.c

RISC-V: Add support for the Zifencei extension

2019-06-25 22:31:21 -07:00

trans_rvm.inc.c

…