11871f53ef
With the new command one can: - assign flexible resources (queues, interrupts) to primary and secondary controllers, - toggle the online/offline state of given controller. Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
575 lines
15 KiB
C
575 lines
15 KiB
C
/*
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* QEMU NVM Express
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*
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* Copyright (c) 2012 Intel Corporation
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* Copyright (c) 2021 Minwoo Im
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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*
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* Authors:
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* Keith Busch <kbusch@kernel.org>
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* Klaus Jensen <k.jensen@samsung.com>
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* Gollu Appalanaidu <anaidu.gollu@samsung.com>
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* Dmitry Fomichev <dmitry.fomichev@wdc.com>
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* Minwoo Im <minwoo.im.dev@gmail.com>
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*
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* This code is licensed under the GNU GPL v2 or later.
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*/
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#ifndef HW_NVME_NVME_H
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#define HW_NVME_NVME_H
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#include "qemu/uuid.h"
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#include "hw/pci/pci.h"
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#include "hw/block/block.h"
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#include "block/nvme.h"
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#define NVME_MAX_CONTROLLERS 256
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#define NVME_MAX_NAMESPACES 256
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#define NVME_EUI64_DEFAULT ((uint64_t)0x5254000000000000)
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QEMU_BUILD_BUG_ON(NVME_MAX_NAMESPACES > NVME_NSID_BROADCAST - 1);
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typedef struct NvmeCtrl NvmeCtrl;
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typedef struct NvmeNamespace NvmeNamespace;
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#define TYPE_NVME_BUS "nvme-bus"
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OBJECT_DECLARE_SIMPLE_TYPE(NvmeBus, NVME_BUS)
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typedef struct NvmeBus {
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BusState parent_bus;
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} NvmeBus;
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#define TYPE_NVME_SUBSYS "nvme-subsys"
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#define NVME_SUBSYS(obj) \
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OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS)
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#define SUBSYS_SLOT_RSVD (void *)0xFFFF
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typedef struct NvmeSubsystem {
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DeviceState parent_obj;
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NvmeBus bus;
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uint8_t subnqn[256];
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char *serial;
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NvmeCtrl *ctrls[NVME_MAX_CONTROLLERS];
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NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1];
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struct {
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char *nqn;
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} params;
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} NvmeSubsystem;
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int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
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void nvme_subsys_unregister_ctrl(NvmeSubsystem *subsys, NvmeCtrl *n);
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static inline NvmeCtrl *nvme_subsys_ctrl(NvmeSubsystem *subsys,
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uint32_t cntlid)
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{
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if (!subsys || cntlid >= NVME_MAX_CONTROLLERS) {
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return NULL;
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}
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if (subsys->ctrls[cntlid] == SUBSYS_SLOT_RSVD) {
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return NULL;
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}
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return subsys->ctrls[cntlid];
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}
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static inline NvmeNamespace *nvme_subsys_ns(NvmeSubsystem *subsys,
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uint32_t nsid)
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{
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if (!subsys || !nsid || nsid > NVME_MAX_NAMESPACES) {
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return NULL;
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}
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return subsys->namespaces[nsid];
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}
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#define TYPE_NVME_NS "nvme-ns"
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#define NVME_NS(obj) \
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OBJECT_CHECK(NvmeNamespace, (obj), TYPE_NVME_NS)
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typedef struct NvmeZone {
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NvmeZoneDescr d;
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uint64_t w_ptr;
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QTAILQ_ENTRY(NvmeZone) entry;
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} NvmeZone;
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typedef struct NvmeNamespaceParams {
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bool detached;
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bool shared;
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uint32_t nsid;
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QemuUUID uuid;
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uint64_t eui64;
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bool eui64_default;
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uint16_t ms;
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uint8_t mset;
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uint8_t pi;
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uint8_t pil;
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uint8_t pif;
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uint16_t mssrl;
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uint32_t mcl;
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uint8_t msrc;
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bool zoned;
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bool cross_zone_read;
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uint64_t zone_size_bs;
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uint64_t zone_cap_bs;
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uint32_t max_active_zones;
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uint32_t max_open_zones;
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uint32_t zd_extension_size;
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uint32_t numzrwa;
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uint64_t zrwas;
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uint64_t zrwafg;
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} NvmeNamespaceParams;
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typedef struct NvmeNamespace {
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DeviceState parent_obj;
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BlockConf blkconf;
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int32_t bootindex;
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int64_t size;
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int64_t moff;
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NvmeIdNs id_ns;
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NvmeIdNsNvm id_ns_nvm;
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NvmeLBAF lbaf;
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unsigned int nlbaf;
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size_t lbasz;
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const uint32_t *iocs;
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uint8_t csi;
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uint16_t status;
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int attached;
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uint8_t pif;
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struct {
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uint16_t zrwas;
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uint16_t zrwafg;
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uint32_t numzrwa;
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} zns;
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QTAILQ_ENTRY(NvmeNamespace) entry;
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NvmeIdNsZoned *id_ns_zoned;
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NvmeZone *zone_array;
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QTAILQ_HEAD(, NvmeZone) exp_open_zones;
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QTAILQ_HEAD(, NvmeZone) imp_open_zones;
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QTAILQ_HEAD(, NvmeZone) closed_zones;
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QTAILQ_HEAD(, NvmeZone) full_zones;
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uint32_t num_zones;
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uint64_t zone_size;
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uint64_t zone_capacity;
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uint32_t zone_size_log2;
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uint8_t *zd_extensions;
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int32_t nr_open_zones;
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int32_t nr_active_zones;
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NvmeNamespaceParams params;
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struct {
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uint32_t err_rec;
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} features;
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} NvmeNamespace;
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static inline uint32_t nvme_nsid(NvmeNamespace *ns)
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{
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if (ns) {
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return ns->params.nsid;
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}
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return 0;
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}
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static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
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{
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return lba << ns->lbaf.ds;
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}
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static inline size_t nvme_m2b(NvmeNamespace *ns, uint64_t lba)
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{
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return ns->lbaf.ms * lba;
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}
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static inline int64_t nvme_moff(NvmeNamespace *ns, uint64_t lba)
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{
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return ns->moff + nvme_m2b(ns, lba);
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}
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static inline bool nvme_ns_ext(NvmeNamespace *ns)
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{
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return !!NVME_ID_NS_FLBAS_EXTENDED(ns->id_ns.flbas);
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}
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static inline NvmeZoneState nvme_get_zone_state(NvmeZone *zone)
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{
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return zone->d.zs >> 4;
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}
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static inline void nvme_set_zone_state(NvmeZone *zone, NvmeZoneState state)
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{
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zone->d.zs = state << 4;
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}
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static inline uint64_t nvme_zone_rd_boundary(NvmeNamespace *ns, NvmeZone *zone)
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{
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return zone->d.zslba + ns->zone_size;
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}
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static inline uint64_t nvme_zone_wr_boundary(NvmeZone *zone)
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{
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return zone->d.zslba + zone->d.zcap;
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}
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static inline bool nvme_wp_is_valid(NvmeZone *zone)
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{
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uint8_t st = nvme_get_zone_state(zone);
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return st != NVME_ZONE_STATE_FULL &&
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st != NVME_ZONE_STATE_READ_ONLY &&
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st != NVME_ZONE_STATE_OFFLINE;
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}
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static inline uint8_t *nvme_get_zd_extension(NvmeNamespace *ns,
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uint32_t zone_idx)
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{
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return &ns->zd_extensions[zone_idx * ns->params.zd_extension_size];
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}
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static inline void nvme_aor_inc_open(NvmeNamespace *ns)
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{
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assert(ns->nr_open_zones >= 0);
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if (ns->params.max_open_zones) {
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ns->nr_open_zones++;
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assert(ns->nr_open_zones <= ns->params.max_open_zones);
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}
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}
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static inline void nvme_aor_dec_open(NvmeNamespace *ns)
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{
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if (ns->params.max_open_zones) {
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assert(ns->nr_open_zones > 0);
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ns->nr_open_zones--;
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}
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assert(ns->nr_open_zones >= 0);
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}
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static inline void nvme_aor_inc_active(NvmeNamespace *ns)
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{
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assert(ns->nr_active_zones >= 0);
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if (ns->params.max_active_zones) {
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ns->nr_active_zones++;
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assert(ns->nr_active_zones <= ns->params.max_active_zones);
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}
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}
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static inline void nvme_aor_dec_active(NvmeNamespace *ns)
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{
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if (ns->params.max_active_zones) {
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assert(ns->nr_active_zones > 0);
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ns->nr_active_zones--;
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assert(ns->nr_active_zones >= ns->nr_open_zones);
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}
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assert(ns->nr_active_zones >= 0);
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}
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void nvme_ns_init_format(NvmeNamespace *ns);
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int nvme_ns_setup(NvmeNamespace *ns, Error **errp);
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void nvme_ns_drain(NvmeNamespace *ns);
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void nvme_ns_shutdown(NvmeNamespace *ns);
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void nvme_ns_cleanup(NvmeNamespace *ns);
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typedef struct NvmeAsyncEvent {
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QTAILQ_ENTRY(NvmeAsyncEvent) entry;
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NvmeAerResult result;
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} NvmeAsyncEvent;
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enum {
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NVME_SG_ALLOC = 1 << 0,
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NVME_SG_DMA = 1 << 1,
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};
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typedef struct NvmeSg {
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int flags;
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union {
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QEMUSGList qsg;
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QEMUIOVector iov;
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};
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} NvmeSg;
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typedef enum NvmeTxDirection {
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NVME_TX_DIRECTION_TO_DEVICE = 0,
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NVME_TX_DIRECTION_FROM_DEVICE = 1,
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} NvmeTxDirection;
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typedef struct NvmeRequest {
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struct NvmeSQueue *sq;
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struct NvmeNamespace *ns;
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BlockAIOCB *aiocb;
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uint16_t status;
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void *opaque;
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NvmeCqe cqe;
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NvmeCmd cmd;
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BlockAcctCookie acct;
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NvmeSg sg;
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QTAILQ_ENTRY(NvmeRequest)entry;
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} NvmeRequest;
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typedef struct NvmeBounceContext {
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NvmeRequest *req;
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struct {
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QEMUIOVector iov;
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uint8_t *bounce;
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} data, mdata;
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} NvmeBounceContext;
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static inline const char *nvme_adm_opc_str(uint8_t opc)
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{
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switch (opc) {
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case NVME_ADM_CMD_DELETE_SQ: return "NVME_ADM_CMD_DELETE_SQ";
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case NVME_ADM_CMD_CREATE_SQ: return "NVME_ADM_CMD_CREATE_SQ";
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case NVME_ADM_CMD_GET_LOG_PAGE: return "NVME_ADM_CMD_GET_LOG_PAGE";
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case NVME_ADM_CMD_DELETE_CQ: return "NVME_ADM_CMD_DELETE_CQ";
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case NVME_ADM_CMD_CREATE_CQ: return "NVME_ADM_CMD_CREATE_CQ";
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case NVME_ADM_CMD_IDENTIFY: return "NVME_ADM_CMD_IDENTIFY";
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case NVME_ADM_CMD_ABORT: return "NVME_ADM_CMD_ABORT";
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case NVME_ADM_CMD_SET_FEATURES: return "NVME_ADM_CMD_SET_FEATURES";
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case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
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case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
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case NVME_ADM_CMD_NS_ATTACHMENT: return "NVME_ADM_CMD_NS_ATTACHMENT";
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case NVME_ADM_CMD_VIRT_MNGMT: return "NVME_ADM_CMD_VIRT_MNGMT";
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case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM";
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default: return "NVME_ADM_CMD_UNKNOWN";
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}
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}
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static inline const char *nvme_io_opc_str(uint8_t opc)
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{
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switch (opc) {
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case NVME_CMD_FLUSH: return "NVME_NVM_CMD_FLUSH";
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case NVME_CMD_WRITE: return "NVME_NVM_CMD_WRITE";
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case NVME_CMD_READ: return "NVME_NVM_CMD_READ";
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case NVME_CMD_COMPARE: return "NVME_NVM_CMD_COMPARE";
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case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES";
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case NVME_CMD_DSM: return "NVME_NVM_CMD_DSM";
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case NVME_CMD_VERIFY: return "NVME_NVM_CMD_VERIFY";
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case NVME_CMD_COPY: return "NVME_NVM_CMD_COPY";
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case NVME_CMD_ZONE_MGMT_SEND: return "NVME_ZONED_CMD_MGMT_SEND";
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case NVME_CMD_ZONE_MGMT_RECV: return "NVME_ZONED_CMD_MGMT_RECV";
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case NVME_CMD_ZONE_APPEND: return "NVME_ZONED_CMD_ZONE_APPEND";
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default: return "NVME_NVM_CMD_UNKNOWN";
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}
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}
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typedef struct NvmeSQueue {
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struct NvmeCtrl *ctrl;
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uint16_t sqid;
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uint16_t cqid;
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uint32_t head;
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uint32_t tail;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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NvmeRequest *io_req;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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QTAILQ_HEAD(, NvmeRequest) out_req_list;
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QTAILQ_ENTRY(NvmeSQueue) entry;
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} NvmeSQueue;
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typedef struct NvmeCQueue {
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struct NvmeCtrl *ctrl;
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uint8_t phase;
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uint16_t cqid;
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uint16_t irq_enabled;
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uint32_t head;
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uint32_t tail;
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uint32_t vector;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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QTAILQ_HEAD(, NvmeSQueue) sq_list;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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} NvmeCQueue;
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#define TYPE_NVME "nvme"
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#define NVME(obj) \
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OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
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typedef struct NvmeParams {
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char *serial;
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uint32_t num_queues; /* deprecated since 5.1 */
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uint32_t max_ioqpairs;
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uint16_t msix_qsize;
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uint32_t cmb_size_mb;
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uint8_t aerl;
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uint32_t aer_max_queued;
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uint8_t mdts;
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uint8_t vsl;
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bool use_intel_id;
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uint8_t zasl;
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bool auto_transition_zones;
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bool legacy_cmb;
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uint8_t sriov_max_vfs;
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uint16_t sriov_vq_flexible;
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uint16_t sriov_vi_flexible;
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uint8_t sriov_max_vq_per_vf;
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uint8_t sriov_max_vi_per_vf;
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} NvmeParams;
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typedef struct NvmeCtrl {
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PCIDevice parent_obj;
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MemoryRegion bar0;
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MemoryRegion iomem;
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NvmeBar bar;
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NvmeParams params;
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NvmeBus bus;
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uint16_t cntlid;
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bool qs_created;
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uint32_t page_size;
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uint16_t page_bits;
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uint16_t max_prp_ents;
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uint16_t cqe_size;
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uint16_t sqe_size;
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uint32_t max_q_ents;
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uint8_t outstanding_aers;
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uint32_t irq_status;
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int cq_pending;
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uint64_t host_timestamp; /* Timestamp sent by the host */
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uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
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uint64_t starttime_ms;
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uint16_t temperature;
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uint8_t smart_critical_warning;
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uint32_t conf_msix_qsize;
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uint32_t conf_ioqpairs;
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struct {
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MemoryRegion mem;
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uint8_t *buf;
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bool cmse;
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hwaddr cba;
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} cmb;
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struct {
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HostMemoryBackend *dev;
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bool cmse;
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hwaddr cba;
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} pmr;
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uint8_t aer_mask;
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NvmeRequest **aer_reqs;
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QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue;
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int aer_queued;
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uint32_t dmrsl;
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/* Namespace ID is started with 1 so bitmap should be 1-based */
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#define NVME_CHANGED_NSID_SIZE (NVME_MAX_NAMESPACES + 1)
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DECLARE_BITMAP(changed_nsids, NVME_CHANGED_NSID_SIZE);
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NvmeSubsystem *subsys;
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NvmeNamespace namespace;
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NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1];
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NvmeSQueue **sq;
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NvmeCQueue **cq;
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NvmeSQueue admin_sq;
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NvmeCQueue admin_cq;
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NvmeIdCtrl id_ctrl;
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struct {
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struct {
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uint16_t temp_thresh_hi;
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uint16_t temp_thresh_low;
|
|
};
|
|
|
|
uint32_t async_config;
|
|
NvmeHostBehaviorSupport hbs;
|
|
} features;
|
|
|
|
NvmePriCtrlCap pri_ctrl_cap;
|
|
NvmeSecCtrlList sec_ctrl_list;
|
|
struct {
|
|
uint16_t vqrfap;
|
|
uint16_t virfap;
|
|
} next_pri_ctrl_cap; /* These override pri_ctrl_cap after reset */
|
|
} NvmeCtrl;
|
|
|
|
typedef enum NvmeResetType {
|
|
NVME_RESET_FUNCTION = 0,
|
|
NVME_RESET_CONTROLLER = 1,
|
|
} NvmeResetType;
|
|
|
|
static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
|
|
{
|
|
if (!nsid || nsid > NVME_MAX_NAMESPACES) {
|
|
return NULL;
|
|
}
|
|
|
|
return n->namespaces[nsid];
|
|
}
|
|
|
|
static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
|
|
{
|
|
NvmeSQueue *sq = req->sq;
|
|
NvmeCtrl *n = sq->ctrl;
|
|
|
|
return n->cq[sq->cqid];
|
|
}
|
|
|
|
static inline NvmeCtrl *nvme_ctrl(NvmeRequest *req)
|
|
{
|
|
NvmeSQueue *sq = req->sq;
|
|
return sq->ctrl;
|
|
}
|
|
|
|
static inline uint16_t nvme_cid(NvmeRequest *req)
|
|
{
|
|
if (!req) {
|
|
return 0xffff;
|
|
}
|
|
|
|
return le16_to_cpu(req->cqe.cid);
|
|
}
|
|
|
|
static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n)
|
|
{
|
|
PCIDevice *pci_dev = &n->parent_obj;
|
|
NvmeCtrl *pf = NVME(pcie_sriov_get_pf(pci_dev));
|
|
|
|
if (pci_is_vf(pci_dev)) {
|
|
return &pf->sec_ctrl_list.sec[pcie_sriov_vf_number(pci_dev)];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static inline NvmeSecCtrlEntry *nvme_sctrl_for_cntlid(NvmeCtrl *n,
|
|
uint16_t cntlid)
|
|
{
|
|
NvmeSecCtrlList *list = &n->sec_ctrl_list;
|
|
uint8_t i;
|
|
|
|
for (i = 0; i < list->numcntl; i++) {
|
|
if (le16_to_cpu(list->sec[i].scid) == cntlid) {
|
|
return &list->sec[i];
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns);
|
|
uint16_t nvme_bounce_data(NvmeCtrl *n, void *ptr, uint32_t len,
|
|
NvmeTxDirection dir, NvmeRequest *req);
|
|
uint16_t nvme_bounce_mdata(NvmeCtrl *n, void *ptr, uint32_t len,
|
|
NvmeTxDirection dir, NvmeRequest *req);
|
|
void nvme_rw_complete_cb(void *opaque, int ret);
|
|
uint16_t nvme_map_dptr(NvmeCtrl *n, NvmeSg *sg, size_t len,
|
|
NvmeCmd *cmd);
|
|
|
|
#endif /* HW_NVME_NVME_H */
|