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69049bcf51
qemu/target/arm
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Peter Maydell 69049bcf51 target/arm: Update feature checks for insns which are "MVE or FP" 
Some v8M instructions are present if either the floating point
extension or MVE is implemented.  Update our implementation of them
to check for MVE as well as for FP.

This is all the insns which use CheckDecodeFaults(ExtType_MveOrFp) or
CheckDecodeFaults(ExtType_MveOrDpFp) in their pseudocode, which are
essentially the loads and stores, moves and sysreg accesses, except
for VMOV_reg_sp and VMOV_reg_dp, which we handle in subsequent
patches because they need a refactor to provide a place to put the
new MVE check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-3-peter.maydell@linaro.org
2021-06-03 16:43:25 +01:00
..
a32-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
a32.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arch_dump.c target/arm: add spaces around operator 2020-11-10 11:03:47 +00:00
arm_ldst.h arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arm-powerctl.c
arm-powerctl.h
cpu64.c target/arm: Enable SVE2 and related extensions 2021-05-25 16:01:44 +01:00
cpu_tcg.c hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
cpu-param.h linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE 2021-02-16 13:06:16 +00:00
cpu-qom.h
cpu.c hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
cpu.h target/arm: Add isar feature check functions for MVE 2021-06-03 16:43:24 +01:00
crypto_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
debug_helper.c
gdbstub64.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
gdbstub.c target/arm: use official org.gnu.gdb.aarch64.sve layout for registers 2021-01-18 10:05:06 +00:00
helper-a64.c target/arm: Add wrapper macros for accessing tbflags 2021-04-30 11:16:50 +01:00
helper-a64.h target/arm: Merge mte_check1, mte_checkN 2021-04-30 11:16:49 +01:00
helper-sve.h target/arm: Implement SVE2 bitwise shift immediate 2021-05-25 16:01:44 +01:00
helper.c target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 2021-05-25 16:01:43 +01:00
helper.h target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
idau.h
internals.h target/arm: Rename mte_probe1 to mte_probe 2021-04-30 11:16:49 +01:00
iwmmxt_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
kvm64.c target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 2021-05-25 16:01:43 +01:00
kvm_arm.h hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
kvm-consts.h
kvm-stub.c
kvm.c hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
m_helper.c target/arm: Use correct SP in M-profile exception return 2021-05-25 16:01:43 +01:00
m-nocp.decode target/arm: Implement new v8.1M VLLDM and VLSTM encodings 2020-12-10 11:44:56 +00:00
machine.c target/arm: Don't migrate CPUARMState.features 2021-02-11 11:50:13 +00:00
meson.build target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
monitor.c target/arm: Add cpu properties to control pauth 2021-01-19 14:38:51 +00:00
mte_helper.c target/arm: Rename mte_probe1 to mte_probe 2021-04-30 11:16:49 +01:00
neon_helper.c target/arm: Split out saturating/rounding shifts from neon 2021-05-25 16:01:43 +01:00
neon-dp.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
neon-ls.decode target/arm: Fix decode of align in VLDST_single 2021-04-30 11:16:49 +01:00
neon-shared.decode target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
op_addsub.h
op_helper.c target/arm: Make WFI a NOP for userspace emulators 2021-05-10 13:24:09 +01:00
pauth_helper.c target/arm: Implement an IMPDEF pauth algorithm 2021-01-19 14:38:51 +00:00
psci.c
sve_helper.c target/arm: Move endian adjustment macros to vec_internal.h 2021-05-25 16:01:44 +01:00
sve.decode target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
syndrome.h target/arm: Split out syndrome.h from internals.h 2021-02-16 13:16:18 +00:00
t16.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
t32.decode target/arm: Implement M-profile "minimal RAS implementation" 2020-12-10 11:44:56 +00:00
tlb_helper.c target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 2021-03-23 14:07:55 +00:00
trace-events docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
trace.h
translate-a32.h target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
translate-a64.c target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
translate-a64.h target/arm: Implement SVE2 XAR 2021-05-25 16:01:44 +01:00
translate-m-nocp.c target/arm: Split m-nocp trans functions into their own file 2021-05-10 13:24:09 +01:00
translate-neon.c target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
translate-sve.c target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
translate-vfp.c target/arm: Update feature checks for insns which are "MVE or FP" 2021-06-03 16:43:25 +01:00
translate.c target/arm: Make sure that commpage's tb->size != 0 2021-05-20 14:19:30 +02:00
translate.h target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h 2021-05-10 13:24:09 +01:00
vec_helper.c target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
vec_internal.h target/arm: Move endian adjustment macros to vec_internal.h 2021-05-25 16:01:44 +01:00
vfp_helper.c target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension 2020-10-20 16:12:01 +01:00
vfp-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
vfp.decode target/arm: Implement VLDR/VSTR system register 2020-12-10 11:44:55 +00:00