Fabian Aggeler 679aa175e8 hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked ... ICDDCR/GICD_CTLR is banked if the GIC has the security extensions, and the S (or only) copy has separate enable bits for Group0 and Group1 enable if the GIC implements interrupt groups. EnableGroup0 (Bit [1]) in GICv1 is architecturally IMPDEF. Since this bit (Enable Non-secure) is present in the integrated GIC of the Cortex-A9 MPCore, we support this bit in our GICv1 implementation too. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-7-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-8-git-send-email-greg.bellows@linaro.org [PMM: rewritten to store the state in a single s->ctlr uint32, with the NS register handled as an alias of bit 1 in that value; added vmstate version bump] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2015-05-12 11:57:17 +01:00
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allwinner-a10-pic.h	hw/intc: add allwinner A10 interrupt controller	2013-12-17 20:12:51 +00:00
arm_gic_common.h	hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked	2015-05-12 11:57:17 +01:00
arm_gic.h
realview_gic.h