423 lines
12 KiB
C
423 lines
12 KiB
C
/*
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* Samsung exynos4210 Pulse Width Modulation Timer
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*
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* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
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* All rights reserved.
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*
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* Evgeny Voevodin <e.voevodin@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "qemu-common.h"
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#include "hw/ptimer.h"
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#include "hw/arm/exynos4210.h"
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//#define DEBUG_PWM
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#ifdef DEBUG_PWM
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#define DPRINTF(fmt, ...) \
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do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \
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## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define EXYNOS4210_PWM_TIMERS_NUM 5
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#define EXYNOS4210_PWM_REG_MEM_SIZE 0x50
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#define TCFG0 0x0000
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#define TCFG1 0x0004
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#define TCON 0x0008
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#define TCNTB0 0x000C
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#define TCMPB0 0x0010
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#define TCNTO0 0x0014
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#define TCNTB1 0x0018
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#define TCMPB1 0x001C
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#define TCNTO1 0x0020
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#define TCNTB2 0x0024
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#define TCMPB2 0x0028
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#define TCNTO2 0x002C
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#define TCNTB3 0x0030
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#define TCMPB3 0x0034
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#define TCNTO3 0x0038
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#define TCNTB4 0x003C
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#define TCNTO4 0x0040
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#define TINT_CSTAT 0x0044
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#define TCNTB(x) (0xC * (x))
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#define TCMPB(x) (0xC * (x) + 1)
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#define TCNTO(x) (0xC * (x) + 2)
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#define GET_PRESCALER(reg, x) (((reg) & (0xFF << (8 * (x)))) >> 8 * (x))
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#define GET_DIVIDER(reg, x) (1 << (((reg) & (0xF << (4 * (x)))) >> (4 * (x))))
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/*
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* Attention! Timer4 doesn't have OUTPUT_INVERTER,
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* so Auto Reload bit is not accessible by macros!
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*/
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#define TCON_TIMER_BASE(x) (((x) ? 1 : 0) * 4 + 4 * (x))
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#define TCON_TIMER_START(x) (1 << (TCON_TIMER_BASE(x) + 0))
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#define TCON_TIMER_MANUAL_UPD(x) (1 << (TCON_TIMER_BASE(x) + 1))
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#define TCON_TIMER_OUTPUT_INV(x) (1 << (TCON_TIMER_BASE(x) + 2))
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#define TCON_TIMER_AUTO_RELOAD(x) (1 << (TCON_TIMER_BASE(x) + 3))
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#define TCON_TIMER4_AUTO_RELOAD (1 << 22)
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#define TINT_CSTAT_STATUS(x) (1 << (5 + (x)))
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#define TINT_CSTAT_ENABLE(x) (1 << (x))
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/* timer struct */
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typedef struct {
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uint32_t id; /* timer id */
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qemu_irq irq; /* local timer irq */
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uint32_t freq; /* timer frequency */
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/* use ptimer.c to represent count down timer */
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ptimer_state *ptimer; /* timer */
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/* registers */
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uint32_t reg_tcntb; /* counter register buffer */
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uint32_t reg_tcmpb; /* compare register buffer */
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struct Exynos4210PWMState *parent;
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} Exynos4210PWM;
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typedef struct Exynos4210PWMState {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t reg_tcfg[2];
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uint32_t reg_tcon;
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uint32_t reg_tint_cstat;
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Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM];
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} Exynos4210PWMState;
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/*** VMState ***/
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static const VMStateDescription vmstate_exynos4210_pwm = {
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.name = "exynos4210.pwm.pwm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(id, Exynos4210PWM),
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VMSTATE_UINT32(freq, Exynos4210PWM),
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VMSTATE_PTIMER(ptimer, Exynos4210PWM),
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VMSTATE_UINT32(reg_tcntb, Exynos4210PWM),
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VMSTATE_UINT32(reg_tcmpb, Exynos4210PWM),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_exynos4210_pwm_state = {
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.name = "exynos4210.pwm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2),
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VMSTATE_UINT32(reg_tcon, Exynos4210PWMState),
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VMSTATE_UINT32(reg_tint_cstat, Exynos4210PWMState),
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VMSTATE_STRUCT_ARRAY(timer, Exynos4210PWMState,
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EXYNOS4210_PWM_TIMERS_NUM, 0,
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vmstate_exynos4210_pwm, Exynos4210PWM),
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VMSTATE_END_OF_LIST()
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}
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};
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/*
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* PWM update frequency
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*/
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static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
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{
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uint32_t freq;
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freq = s->timer[id].freq;
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if (id > 1) {
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s->timer[id].freq = 24000000 /
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((GET_PRESCALER(s->reg_tcfg[0], 1) + 1) *
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(GET_DIVIDER(s->reg_tcfg[1], id)));
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} else {
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s->timer[id].freq = 24000000 /
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((GET_PRESCALER(s->reg_tcfg[0], 0) + 1) *
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(GET_DIVIDER(s->reg_tcfg[1], id)));
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}
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if (freq != s->timer[id].freq) {
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ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
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DPRINTF("freq=%dHz\n", s->timer[id].freq);
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}
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}
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/*
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* Counter tick handler
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*/
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static void exynos4210_pwm_tick(void *opaque)
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{
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Exynos4210PWM *s = (Exynos4210PWM *)opaque;
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Exynos4210PWMState *p = (Exynos4210PWMState *)s->parent;
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uint32_t id = s->id;
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bool cmp;
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DPRINTF("timer %d tick\n", id);
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/* set irq status */
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p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
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/* raise IRQ */
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if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
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DPRINTF("timer %d IRQ\n", id);
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qemu_irq_raise(p->timer[id].irq);
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}
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/* reload timer */
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if (id != 4) {
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cmp = p->reg_tcon & TCON_TIMER_AUTO_RELOAD(id);
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} else {
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cmp = p->reg_tcon & TCON_TIMER4_AUTO_RELOAD;
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}
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if (cmp) {
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DPRINTF("auto reload timer %d count to %x\n", id,
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p->timer[id].reg_tcntb);
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ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
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ptimer_run(p->timer[id].ptimer, 1);
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} else {
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/* stop timer, set status to STOP, see Basic Timer Operation */
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p->reg_tcon &= ~TCON_TIMER_START(id);
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ptimer_stop(p->timer[id].ptimer);
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}
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}
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/*
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* PWM Read
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*/
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static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
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uint32_t value = 0;
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int index;
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switch (offset) {
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case TCFG0: case TCFG1:
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index = (offset - TCFG0) >> 2;
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value = s->reg_tcfg[index];
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break;
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case TCON:
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value = s->reg_tcon;
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break;
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case TCNTB0: case TCNTB1:
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case TCNTB2: case TCNTB3: case TCNTB4:
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index = (offset - TCNTB0) / 0xC;
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value = s->timer[index].reg_tcntb;
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break;
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case TCMPB0: case TCMPB1:
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case TCMPB2: case TCMPB3:
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index = (offset - TCMPB0) / 0xC;
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value = s->timer[index].reg_tcmpb;
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break;
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case TCNTO0: case TCNTO1:
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case TCNTO2: case TCNTO3: case TCNTO4:
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index = (offset == TCNTO4) ? 4 : (offset - TCNTO0) / 0xC;
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value = ptimer_get_count(s->timer[index].ptimer);
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break;
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case TINT_CSTAT:
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value = s->reg_tint_cstat;
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break;
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default:
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fprintf(stderr,
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"[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
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offset);
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break;
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}
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return value;
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}
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/*
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* PWM Write
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*/
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static void exynos4210_pwm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
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int index;
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uint32_t new_val;
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int i;
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switch (offset) {
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case TCFG0: case TCFG1:
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index = (offset - TCFG0) >> 2;
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s->reg_tcfg[index] = value;
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/* update timers frequencies */
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for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
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exynos4210_pwm_update_freq(s, s->timer[i].id);
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}
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break;
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case TCON:
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for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
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if ((value & TCON_TIMER_MANUAL_UPD(i)) >
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(s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) {
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/*
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* TCNTB and TCMPB are loaded into TCNT and TCMP.
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* Update timers.
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*/
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/* this will start timer to run, this ok, because
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* during processing start bit timer will be stopped
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* if needed */
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ptimer_set_count(s->timer[i].ptimer, s->timer[i].reg_tcntb);
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DPRINTF("set timer %d count to %x\n", i,
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s->timer[i].reg_tcntb);
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}
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if ((value & TCON_TIMER_START(i)) >
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(s->reg_tcon & TCON_TIMER_START(i))) {
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/* changed to start */
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ptimer_run(s->timer[i].ptimer, 1);
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DPRINTF("run timer %d\n", i);
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}
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if ((value & TCON_TIMER_START(i)) <
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(s->reg_tcon & TCON_TIMER_START(i))) {
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/* changed to stop */
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ptimer_stop(s->timer[i].ptimer);
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DPRINTF("stop timer %d\n", i);
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}
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}
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s->reg_tcon = value;
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break;
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case TCNTB0: case TCNTB1:
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case TCNTB2: case TCNTB3: case TCNTB4:
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index = (offset - TCNTB0) / 0xC;
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s->timer[index].reg_tcntb = value;
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break;
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case TCMPB0: case TCMPB1:
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case TCMPB2: case TCMPB3:
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index = (offset - TCMPB0) / 0xC;
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s->timer[index].reg_tcmpb = value;
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break;
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case TINT_CSTAT:
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new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value);
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new_val &= ~(0x3E0 & value);
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for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
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if ((new_val & TINT_CSTAT_STATUS(i)) <
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(s->reg_tint_cstat & TINT_CSTAT_STATUS(i))) {
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qemu_irq_lower(s->timer[i].irq);
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}
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}
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s->reg_tint_cstat = new_val;
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break;
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default:
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fprintf(stderr,
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"[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
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offset);
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break;
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}
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}
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/*
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* Set default values to timer fields and registers
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*/
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static void exynos4210_pwm_reset(DeviceState *d)
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{
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Exynos4210PWMState *s = (Exynos4210PWMState *)d;
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int i;
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s->reg_tcfg[0] = 0x0101;
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s->reg_tcfg[1] = 0x0;
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s->reg_tcon = 0;
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s->reg_tint_cstat = 0;
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for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
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s->timer[i].reg_tcmpb = 0;
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s->timer[i].reg_tcntb = 0;
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exynos4210_pwm_update_freq(s, s->timer[i].id);
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ptimer_stop(s->timer[i].ptimer);
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}
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}
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static const MemoryRegionOps exynos4210_pwm_ops = {
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.read = exynos4210_pwm_read,
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.write = exynos4210_pwm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/*
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* PWM timer initialization
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*/
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static int exynos4210_pwm_init(SysBusDevice *dev)
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{
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Exynos4210PWMState *s = FROM_SYSBUS(Exynos4210PWMState, dev);
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int i;
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QEMUBH *bh;
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for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
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bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]);
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sysbus_init_irq(dev, &s->timer[i].irq);
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s->timer[i].ptimer = ptimer_init(bh);
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s->timer[i].id = i;
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s->timer[i].parent = s;
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}
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memory_region_init_io(&s->iomem, &exynos4210_pwm_ops, s, "exynos4210-pwm",
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EXYNOS4210_PWM_REG_MEM_SIZE);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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static void exynos4210_pwm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = exynos4210_pwm_init;
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dc->reset = exynos4210_pwm_reset;
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dc->vmsd = &vmstate_exynos4210_pwm_state;
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}
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static const TypeInfo exynos4210_pwm_info = {
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.name = "exynos4210.pwm",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Exynos4210PWMState),
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.class_init = exynos4210_pwm_class_init,
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};
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static void exynos4210_pwm_register_types(void)
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{
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type_register_static(&exynos4210_pwm_info);
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}
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type_init(exynos4210_pwm_register_types)
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