Atish Patra 66b1205bc5 RISC-V: Copy the fdt in dram instead of ROM ... Currently, the fdt is copied to the ROM after the reset vector. The firmware has to copy it to DRAM. Instead of this, directly copy the device tree to a pre-computed dram address. The device tree load address should be as far as possible from kernel and initrd images. That's why it is kept at the end of the DRAM or 4GB whichever is lesser. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-3-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-13 17:25:37 -07:00
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boot.h	RISC-V: Copy the fdt in dram instead of ROM	2020-07-13 17:25:37 -07:00
opentitan.h	riscv/opentitan: Connect the UART device	2020-06-19 08:24:07 -07:00
riscv_hart.h	riscv: hart: Add a "hartid-base" property to RISC-V hart array	2019-09-17 08:42:47 -07:00
riscv_htif.h	Clean up inclusion of sysemu/sysemu.h	2019-08-16 13:31:53 +02:00
sifive_clint.h	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	2020-02-27 13:46:37 -08:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e_prci.h	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.h	sifive_e: Support the revB machine	2020-06-19 08:24:07 -07:00
sifive_gpio.h	hw/riscv: sifive_gpio: Add a new 'ngpio' property	2020-06-19 08:24:07 -07:00
sifive_plic.h	riscv: plic: Remove unused interrupt functions	2019-09-17 08:42:42 -07:00
sifive_test.h	riscv: sifive_test: Add reset functionality	2019-09-17 08:42:44 -07:00
sifive_u_otp.h	riscv: sifive: Implement a model for SiFive FU540 OTP	2019-09-17 08:42:49 -07:00
sifive_u_prci.h	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	2019-09-17 08:42:48 -07:00
sifive_u.h	hw/riscv: sifive_u: Add a dummy DDR memory controller device	2020-06-19 08:25:27 -07:00
sifive_uart.h	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00
spike.h	hw/riscv: spike: Remove deprecated ISA specific machines	2020-06-03 09:11:51 -07:00
virt.h	riscv: virt: Use Goldfish RTC device	2020-02-10 12:01:38 -08:00