668bb9b755
Implement htstate in the obvious way. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/847 Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
69 lines
2.5 KiB
Plaintext
69 lines
2.5 KiB
Plaintext
# SPDX-License-Identifier: LGPL-2.0+
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#
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# Sparc instruction decode definitions.
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# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
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##
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## Major Opcodes 00 and 01 -- branches, call, and sethi.
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##
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&bcc i a cond cc
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BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
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Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
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FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
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FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
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%d16 20:s2 0:14
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BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
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NCP 00 - ---- 111 ---------------------- # CBcc
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SETHI 00 rd:5 100 i:22
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CALL 01 i:s30
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{
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[
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STBAR 10 00000 101000 01111 0 0000000000000
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MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
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RDCCR 10 rd:5 101000 00010 0 0000000000000
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RDASI 10 rd:5 101000 00011 0 0000000000000
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RDTICK 10 rd:5 101000 00100 0 0000000000000
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RDPC 10 rd:5 101000 00101 0 0000000000000
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RDFPRS 10 rd:5 101000 00110 0 0000000000000
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RDASR17 10 rd:5 101000 10001 0 0000000000000
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RDGSR 10 rd:5 101000 10011 0 0000000000000
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RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
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RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
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RDSTICK 10 rd:5 101000 11000 0 0000000000000
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RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000
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RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000
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]
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# Before v8, all rs1 accepted; otherwise rs1==0.
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RDY 10 rd:5 101000 rs1:5 0 0000000000000
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}
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{
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RDPSR 10 rd:5 101001 00000 0 0000000000000
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RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000
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}
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RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000
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RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000
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RDHPR_htba 10 rd:5 101001 00101 0 0000000000000
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RDHPR_hver 10 rd:5 101001 00110 0 0000000000000
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RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000
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Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
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{
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# For v7, the entire simm13 field is present, but masked to 7 bits.
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# For v8, [12:7] are reserved. However, a compatibility note for
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# the Tcc insn in the v9 manual suggests that the v8 reserved field
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# was ignored and did not produce traps.
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Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
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# For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
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# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
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Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
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}
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