Richard Henderson 665b90d8a4 target/riscv: Use riscv_csrrw_debug for cpu_dump ... Use the official debug read interface to the csrs, rather than referencing the env slots directly. Put the list of csrs to dump into a table. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-22 23:35:47 +10:00
..
insn_trans	target/riscv: Use gen_shift*_per_ol for RVB, RVI	2021-10-22 23:35:47 +10:00
arch_dump.c
bitmanip_helper.c	target/riscv: Add rev8 instruction, removing grev/grevi	2021-10-07 08:41:33 +10:00
cpu_bits.h	target/riscv: Create RISCVMXL enumeration	2021-10-22 07:47:51 +10:00
cpu_helper.c	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	2021-10-22 07:47:51 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Use riscv_csrrw_debug for cpu_dump	2021-10-22 23:35:47 +10:00
cpu.h	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	2021-10-22 07:47:51 +10:00
csr.c	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	2021-10-22 07:47:51 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
helper.h	target/riscv: Add rev8 instruction, removing grev/grevi	2021-10-07 08:41:33 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: Remove RVB (replaced by Zb[abcs])	2021-10-07 08:41:33 +10:00
instmap.h
internals.h
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
machine.c	target/riscv: Split misa.mxl and misa.ext	2021-10-22 07:47:51 +10:00
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
op_helper.c	target/riscv: Reorg csr instructions	2021-09-01 11:59:12 +10:00
pmp.c	target/riscv: pmp: Fix some typos	2021-07-15 08:56:00 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h
translate.c	target/riscv: Use gen_shift*_per_ol for RVB, RVI	2021-10-22 23:35:47 +10:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00