722f1352b6
This adds the QSPI2 controller to the SoC, and connects an SD
card to it. The generation of corresponding device tree source
fragment is also added.
Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
Note subsequent payload is stored in the SD card image.
$ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \
-bios u-boot-spl.bin -drive file=sdcard.img,if=sd
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
69 lines
1.3 KiB
Plaintext
69 lines
1.3 KiB
Plaintext
config IBEX
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bool
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config MICROCHIP_PFSOC
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bool
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select CADENCE_SDHCI
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select MCHP_PFSOC_DMC
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select MCHP_PFSOC_IOSCB
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select MCHP_PFSOC_MMUART
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select MCHP_PFSOC_SYSREG
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select MSI_NONBROKEN
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select SIFIVE_CLINT
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select UNIMP
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config OPENTITAN
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bool
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select IBEX
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select UNIMP
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config RISCV_VIRT
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bool
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imply PCI_DEVICES
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imply TEST_DEVICES
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select GOLDFISH_RTC
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select MSI_NONBROKEN
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select PCI
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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select SERIAL
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select SIFIVE_CLINT
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select SIFIVE_PLIC
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select SIFIVE_TEST
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select VIRTIO_MMIO
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config SIFIVE_E
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bool
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select MSI_NONBROKEN
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select SIFIVE_CLINT
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select SIFIVE_GPIO
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select SIFIVE_PLIC
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select SIFIVE_UART
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select SIFIVE_E_PRCI
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select UNIMP
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config SIFIVE_U
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bool
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select CADENCE
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select MSI_NONBROKEN
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select SIFIVE_CLINT
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select SIFIVE_GPIO
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select SIFIVE_SPI
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select SIFIVE_UART
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select SIFIVE_U_OTP
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select SIFIVE_U_PRCI
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select SSI_M25P80
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select SSI_SD
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select UNIMP
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config SPIKE
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bool
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select HTIF
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select MSI_NONBROKEN
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select SIFIVE_CLINT
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select SIFIVE_PLIC
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