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Markus Armbruster 06e2b0107f riscv: Clean up includes 
This commit was created with scripts/clean-includes.

All .c should include qemu/osdep.h first.  The script performs three
related cleanups:

* Ensure .c files include qemu/osdep.h first.
* Including it in a .h is redundant, since the .c  already includes
  it.  Drop such inclusions.
* Likewise, including headers qemu/osdep.h includes is redundant.
  Drop these, too.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20230202133830.2152150-15-armbru@redhat.com>
2023-02-08 07:28:05 +01:00
..
insn_trans
target/riscv: fix ctzw behavior
2023-02-07 08:19:23 +10:00
arch_dump.c
…
bitmanip_helper.c
…
common-semi-target.h
…
cpu_bits.h
target/riscv: Add smstateen support
2023-01-06 10:42:55 +10:00
cpu_helper.c
target/riscv: set tval for triggered watchpoints
2023-02-07 08:19:23 +10:00
cpu_user.h
…
cpu_vendorid.h
RISC-V: Add initial support for T-Head C906
2023-02-07 08:19:23 +10:00
cpu-param.h
…
cpu.c
RISC-V: Adding XTheadFmv ISA extension
2023-02-07 08:19:23 +10:00
cpu.h
RISC-V: Adding XTheadFmv ISA extension
2023-02-07 08:19:23 +10:00
crypto_helper.c
…
csr.c
target/riscv: Update VS timer whenever htimedelta changes
2023-02-07 08:19:22 +10:00
debug.c
target/riscv: set tval for triggered watchpoints
2023-02-07 08:19:23 +10:00
debug.h
target/riscv: Add itrigger support when icount is enabled
2023-01-06 10:42:55 +10:00
fpu_helper.c
target/riscv: Remove helper_set_rod_rounding_mode
2023-01-20 10:14:14 +10:00
gdbstub.c
…
helper.h
RISC-V: Adding XTheadSync ISA extension
2023-02-07 08:19:23 +10:00
insn16.decode
…
insn32.decode
RISC-V: Add Zawrs ISA extension support
2023-01-06 10:42:55 +10:00
instmap.h
…
internals.h
…
Kconfig
…
kvm_riscv.h
…
kvm-stub.c
…
kvm.c
target/riscv: fix SBI getchar handler for KVM
2023-02-07 08:19:23 +10:00
m128_helper.c
…
machine.c
hw/char: riscv_htif: Move registers from CPUArchState to HTIFState
2023-01-20 10:14:13 +10:00
meson.build
RISC-V: Adding XTheadCmo ISA extension
2023-02-07 08:19:23 +10:00
monitor.c
bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx
2023-01-18 11:14:34 +01:00
op_helper.c
RISC-V: Adding XTheadSync ISA extension
2023-02-07 08:19:23 +10:00
pmp.c
target/riscv: Fix PMP propagation for tlb
2023-01-06 10:42:55 +10:00
pmp.h
target/riscv: Fix PMP propagation for tlb
2023-01-06 10:42:55 +10:00
pmu.c
…
pmu.h
riscv: Clean up includes
2023-02-08 07:28:05 +01:00
sbi_ecall_interface.h
…
time_helper.c
target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
2023-02-07 08:19:23 +10:00
time_helper.h
…
trace-events
…
trace.h
…
translate.c
target/riscv: fix for virtual instr exception
2023-02-07 08:19:23 +10:00
vector_helper.c
cleanup: Tweak and re-run return_directly.cocci
2022-12-14 16:19:35 +01:00
xthead.decode
RISC-V: Adding XTheadFmv ISA extension
2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
…