edf5ca5dbe
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
219 lines
6.4 KiB
C
219 lines
6.4 KiB
C
/*
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* QEMU sPAPR PCI host for VFIO
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*
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* Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License,
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* or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include <linux/vfio.h>
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#include "hw/ppc/spapr.h"
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#include "hw/pci-host/spapr.h"
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#include "hw/pci/msix.h"
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#include "hw/pci/pci_device.h"
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#include "hw/vfio/vfio.h"
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#include "qemu/error-report.h"
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bool spapr_phb_eeh_available(SpaprPhbState *sphb)
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{
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return vfio_eeh_as_ok(&sphb->iommu_as);
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}
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static void spapr_phb_vfio_eeh_reenable(SpaprPhbState *sphb)
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{
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vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_ENABLE);
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}
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void spapr_phb_vfio_reset(DeviceState *qdev)
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{
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/*
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* The PE might be in frozen state. To reenable the EEH
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* functionality on it will clean the frozen state, which
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* ensures that the contained PCI devices will work properly
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* after reboot.
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*/
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spapr_phb_vfio_eeh_reenable(SPAPR_PCI_HOST_BRIDGE(qdev));
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}
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static void spapr_eeh_pci_find_device(PCIBus *bus, PCIDevice *pdev,
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void *opaque)
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{
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bool *found = opaque;
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if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
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*found = true;
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}
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}
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int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
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unsigned int addr, int option)
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{
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uint32_t op;
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int ret;
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switch (option) {
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case RTAS_EEH_DISABLE:
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op = VFIO_EEH_PE_DISABLE;
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break;
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case RTAS_EEH_ENABLE: {
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PCIHostState *phb;
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bool found = false;
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/*
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* The EEH functionality is enabled per sphb level instead of
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* per PCI device. We have already identified this specific sphb
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* based on buid passed as argument to ibm,set-eeh-option rtas
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* call. Now we just need to check the validity of the PCI
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* pass-through devices (vfio-pci) under this sphb bus.
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* We have already validated that all the devices under this sphb
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* are from same iommu group (within same PE) before comming here.
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*
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* Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh:
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* Rework device EEH PE determination") kernel would call
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* eeh-set-option for each device in the PE using the device's
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* config_address as the argument rather than the PE address.
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* Hence if we check validity of supplied config_addr whether
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* it matches to this PHB will cause issues with older kernel
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* versions v5.9 and older. If we return an error from
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* eeh-set-option when the argument isn't a valid PE address
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* then older kernels (v5.9 and older) will interpret that as
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* EEH not being supported.
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*/
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phb = PCI_HOST_BRIDGE(sphb);
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pci_for_each_device(phb->bus, (addr >> 16) & 0xFF,
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spapr_eeh_pci_find_device, &found);
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if (!found) {
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return RTAS_OUT_PARAM_ERROR;
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}
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op = VFIO_EEH_PE_ENABLE;
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break;
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}
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case RTAS_EEH_THAW_IO:
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op = VFIO_EEH_PE_UNFREEZE_IO;
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break;
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case RTAS_EEH_THAW_DMA:
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op = VFIO_EEH_PE_UNFREEZE_DMA;
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break;
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default:
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return RTAS_OUT_PARAM_ERROR;
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}
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ret = vfio_eeh_as_op(&sphb->iommu_as, op);
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if (ret < 0) {
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return RTAS_OUT_HW_ERROR;
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}
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return RTAS_OUT_SUCCESS;
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}
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int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state)
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{
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int ret;
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ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_GET_STATE);
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if (ret < 0) {
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return RTAS_OUT_PARAM_ERROR;
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}
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*state = ret;
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return RTAS_OUT_SUCCESS;
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}
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static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus,
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PCIDevice *pdev,
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void *opaque)
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{
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/* Check if the device is VFIO PCI device */
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if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
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return;
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}
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/*
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* The MSIx table will be cleaned out by reset. We need
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* disable it so that it can be reenabled properly. Also,
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* the cached MSIx table should be cleared as it's not
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* reflecting the contents in hardware.
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*/
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if (msix_enabled(pdev)) {
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uint16_t flags;
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flags = pci_host_config_read_common(pdev,
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pdev->msix_cap + PCI_MSIX_FLAGS,
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pci_config_size(pdev), 2);
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flags &= ~PCI_MSIX_FLAGS_ENABLE;
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pci_host_config_write_common(pdev,
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pdev->msix_cap + PCI_MSIX_FLAGS,
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pci_config_size(pdev), flags, 2);
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}
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msix_reset(pdev);
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}
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static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque)
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{
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pci_for_each_device_under_bus(bus, spapr_phb_vfio_eeh_clear_dev_msix,
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NULL);
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}
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static void spapr_phb_vfio_eeh_pre_reset(SpaprPhbState *sphb)
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{
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PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
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pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL);
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}
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int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
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{
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uint32_t op;
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int ret;
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switch (option) {
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case RTAS_SLOT_RESET_DEACTIVATE:
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op = VFIO_EEH_PE_RESET_DEACTIVATE;
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break;
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case RTAS_SLOT_RESET_HOT:
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spapr_phb_vfio_eeh_pre_reset(sphb);
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op = VFIO_EEH_PE_RESET_HOT;
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break;
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case RTAS_SLOT_RESET_FUNDAMENTAL:
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spapr_phb_vfio_eeh_pre_reset(sphb);
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op = VFIO_EEH_PE_RESET_FUNDAMENTAL;
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break;
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default:
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return RTAS_OUT_PARAM_ERROR;
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}
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ret = vfio_eeh_as_op(&sphb->iommu_as, op);
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if (ret < 0) {
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return RTAS_OUT_HW_ERROR;
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}
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return RTAS_OUT_SUCCESS;
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}
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int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
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{
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int ret;
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ret = vfio_eeh_as_op(&sphb->iommu_as, VFIO_EEH_PE_CONFIGURE);
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if (ret < 0) {
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return RTAS_OUT_PARAM_ERROR;
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}
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return RTAS_OUT_SUCCESS;
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}
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