Ira Weiny 64fdad5e67 cxl/cdat: Fix header sum value in CDAT checksum ... The addition of the DCD support for CXL type-3 devices extended the CDAT table large enough that the checksum being returned was incorrect.[1] This was because the checksum value was using the header length field rather than each of the 4 bytes of the length field. This was previously not seen because the length of the CDAT data was less than 256 thus resulting in an equivalent checksum value. Properly calculate the checksum for the CDAT header. [1] https://lore.kernel.org/all/20231116-fix-cdat-devm-free-v1-1-b148b40707d7@intel.com/ Fixes: aba578bdac ("hw/cxl/cdat: CXL CDAT Data Object Exchange implementation") Cc: Huai-Cheng Kuo <hchkuo@avery-design.com.tw> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126120132.24248-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2024-02-14 06:09:32 -05:00
..
cxl-cdat.c	cxl/cdat: Fix header sum value in CDAT checksum	2024-02-14 06:09:32 -05:00
cxl-component-utils.c	hw/cxl: spelling fixes: limitaions, potentialy, intialized	2023-11-15 11:09:17 +03:00
cxl-device-utils.c	hw/cxl/mbox: Wire up interrupts for background completion	2023-11-07 03:39:11 -05:00
cxl-events.c	cxl: Clean up includes	2024-01-30 21:20:20 +03:00
cxl-host-stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
cxl-host.c	hw/cxl: Support 4 HDM decoders at all levels of topology	2023-10-04 18:15:06 -04:00
cxl-mailbox-utils.c	hw/cxl: spelling fixes: limitaions, potentialy, intialized	2023-11-15 11:09:17 +03:00
Kconfig
meson.build	meson: remove CONFIG_ALL	2023-12-31 09:11:28 +01:00
switch-mailbox-cci.c	hw/cxl: Add a switch mailbox CCI function	2023-11-07 03:39:11 -05:00