4c5b10b7b6
Hi, Kevin and I have agreed on the approach for this one now. So here is the latest version of the patch for QEMU, submitting e820 reservation entries via fw_cfg. Cheers, Jes Use qemu-cfg to provide the BIOS with an optional table of e820 entries. Notify the BIOS of the location of the TSS+EPT range to by reserving it via the e820 table. This matches a corresponding patch for Seabios, however older versions of Seabios will default to the hardcoded address range and stay compatible with current QEMU. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
164 lines
4.5 KiB
C
164 lines
4.5 KiB
C
#ifndef HW_PC_H
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#define HW_PC_H
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#include "qemu-common.h"
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/* PC-style peripherals (also used by other machines). */
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/* serial.c */
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SerialState *serial_init(int base, qemu_irq irq, int baudbase,
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CharDriverState *chr);
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SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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qemu_irq irq, int baudbase,
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CharDriverState *chr, int ioregister);
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SerialState *serial_isa_init(int index, CharDriverState *chr);
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void serial_set_frequency(SerialState *s, uint32_t frequency);
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/* parallel.c */
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typedef struct ParallelState ParallelState;
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ParallelState *parallel_init(int index, CharDriverState *chr);
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ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
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/* i8259.c */
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typedef struct PicState2 PicState2;
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extern PicState2 *isa_pic;
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void pic_set_irq(int irq, int level);
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void pic_set_irq_new(void *opaque, int irq, int level);
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qemu_irq *i8259_init(qemu_irq parent_irq);
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int pic_read_irq(PicState2 *s);
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void pic_update_irq(PicState2 *s);
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uint32_t pic_intack_read(PicState2 *s);
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void pic_info(Monitor *mon);
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void irq_info(Monitor *mon);
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/* APIC */
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typedef struct IOAPICState IOAPICState;
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode);
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int apic_init(CPUState *env);
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int apic_accept_pic_intr(CPUState *env);
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void apic_deliver_pic_intr(CPUState *env, int level);
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int apic_get_interrupt(CPUState *env);
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qemu_irq *ioapic_init(void);
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void ioapic_set_irq(void *opaque, int vector, int level);
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void apic_reset_irq_delivered(void);
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int apic_get_irq_delivered(void);
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/* i8254.c */
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#define PIT_FREQ 1193182
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typedef struct PITState PITState;
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PITState *pit_init(int base, qemu_irq irq);
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void pit_set_gate(PITState *pit, int channel, int val);
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int pit_get_gate(PITState *pit, int channel);
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int pit_get_initial_count(PITState *pit, int channel);
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int pit_get_mode(PITState *pit, int channel);
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int pit_get_out(PITState *pit, int channel, int64_t current_time);
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void hpet_pit_disable(void);
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void hpet_pit_enable(void);
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/* vmport.c */
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void vmport_init(void);
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void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
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/* vmmouse.c */
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void *vmmouse_init(void *m);
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/* pckbd.c */
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void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
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void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
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target_phys_addr_t base, ram_addr_t size,
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target_phys_addr_t mask);
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/* mc146818rtc.c */
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typedef struct RTCState RTCState;
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RTCState *rtc_init(int base_year);
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void rtc_set_memory(RTCState *s, int addr, int val);
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void rtc_set_date(RTCState *s, const struct tm *tm);
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void cmos_set_s3_resume(void);
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/* pc.c */
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extern int fd_bootchk;
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void ioport_set_a20(int enable);
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int ioport_get_a20(void);
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/* acpi.c */
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extern int acpi_enabled;
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extern char *acpi_tables;
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extern size_t acpi_tables_len;
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void acpi_bios_init(void);
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int acpi_table_add(const char *table_desc);
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/* acpi_piix.c */
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq);
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void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
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void piix4_acpi_system_hot_add_init(PCIBus *bus);
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/* hpet.c */
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extern int no_hpet;
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/* pcspk.c */
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void pcspk_init(PITState *);
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int pcspk_audio_init(qemu_irq *pic);
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/* piix_pci.c */
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struct PCII440FXState;
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typedef struct PCII440FXState PCII440FXState;
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PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic);
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void i440fx_set_smm(PCII440FXState *d, int val);
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void i440fx_init_memory_mappings(PCII440FXState *d);
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/* piix4.c */
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extern PCIDevice *piix4_dev;
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int piix4_init(PCIBus *bus, int devfn);
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/* vga.c */
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enum vga_retrace_method {
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VGA_RETRACE_DUMB,
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VGA_RETRACE_PRECISE
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};
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extern enum vga_retrace_method vga_retrace_method;
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int isa_vga_init(void);
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int pci_vga_init(PCIBus *bus,
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unsigned long vga_bios_offset, int vga_bios_size);
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int isa_vga_mm_init(target_phys_addr_t vram_base,
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target_phys_addr_t ctrl_base, int it_shift);
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/* cirrus_vga.c */
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void pci_cirrus_vga_init(PCIBus *bus);
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void isa_cirrus_vga_init(void);
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/* ne2000.c */
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void isa_ne2000_init(int base, int irq, NICInfo *nd);
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int cpu_is_bsp(CPUState *env);
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/* e820 types */
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#define E820_RAM 1
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#define E820_RESERVED 2
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#define E820_ACPI 3
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#define E820_NVS 4
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#define E820_UNUSABLE 5
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int e820_add_entry(uint64_t, uint64_t, uint32_t);
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#endif
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