88e74b6122
There are several problems here that can result in soft lockup,
depending on exactly where an interrupt or exception is delivered:
Include BIMM_FLAG in IFLAGS_TB_MASK, since it needs to follow D_FLAG.
Ensure that iflags is 0 when entering an interrupt/exception handler.
Add mb_cpu_synchronize_from_tb to restore iflags from tb->flags.
The change to t_sync_flags is cosmetic, but makes the code clearer.
This fixes the reported regression in acceptance/replay_kernel.py.
Fixes: 683a247ed7 ("target/microblaze: Store "current" iflags in insn_start")
Tested-by: Thomas Huth <thuth@redhat.com>
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200904190842.2282109-2-richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
365 lines
12 KiB
C
365 lines
12 KiB
C
/*
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* QEMU MicroBlaze CPU
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*
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* Copyright (c) 2009 Edgar E. Iglesias
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu/module.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "exec/exec-all.h"
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#include "fpu/softfloat-helpers.h"
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static const struct {
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const char *name;
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uint8_t version_id;
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} mb_cpu_lookup[] = {
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/* These key value are as per MBV field in PVR0 */
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{"5.00.a", 0x01},
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{"5.00.b", 0x02},
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{"5.00.c", 0x03},
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{"6.00.a", 0x04},
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{"6.00.b", 0x06},
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{"7.00.a", 0x05},
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{"7.00.b", 0x07},
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{"7.10.a", 0x08},
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{"7.10.b", 0x09},
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{"7.10.c", 0x0a},
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{"7.10.d", 0x0b},
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{"7.20.a", 0x0c},
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{"7.20.b", 0x0d},
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{"7.20.c", 0x0e},
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{"7.20.d", 0x0f},
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{"7.30.a", 0x10},
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{"7.30.b", 0x11},
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{"8.00.a", 0x12},
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{"8.00.b", 0x13},
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{"8.10.a", 0x14},
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{"8.20.a", 0x15},
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{"8.20.b", 0x16},
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{"8.30.a", 0x17},
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{"8.40.a", 0x18},
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{"8.40.b", 0x19},
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{"8.50.a", 0x1A},
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{"9.0", 0x1B},
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{"9.1", 0x1D},
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{"9.2", 0x1F},
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{"9.3", 0x20},
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{"9.4", 0x21},
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{"9.5", 0x22},
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{"9.6", 0x23},
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{"10.0", 0x24},
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{NULL, 0},
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};
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/* If no specific version gets selected, default to the following. */
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#define DEFAULT_CPU_VERSION "10.0"
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static void mb_cpu_set_pc(CPUState *cs, vaddr value)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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cpu->env.pc = value;
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/* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
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cpu->env.iflags = 0;
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}
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static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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cpu->env.pc = tb->pc;
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cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
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}
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static bool mb_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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}
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#ifndef CONFIG_USER_ONLY
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static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
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{
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MicroBlazeCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
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if (level) {
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cpu_interrupt(cs, type);
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} else {
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cpu_reset_interrupt(cs, type);
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}
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}
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#endif
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static void mb_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
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CPUMBState *env = &cpu->env;
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mcc->parent_reset(dev);
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memset(env, 0, offsetof(CPUMBState, end_reset_fields));
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env->res_addr = RES_ADDR_NONE;
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/* Disable stack protector. */
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env->shr = ~0;
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env->pc = cpu->cfg.base_vectors;
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#if defined(CONFIG_USER_ONLY)
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/* start in user mode with interrupts enabled. */
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mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
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#else
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mb_cpu_write_msr(env, 0);
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mmu_init(&env->mmu);
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env->mmu.c_mmu = 3;
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env->mmu.c_mmu_tlb_access = 3;
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env->mmu.c_mmu_zones = 16;
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env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
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#endif
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}
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static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_arch_microblaze;
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info->print_insn = print_insn_microblaze;
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}
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static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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uint8_t version_code = 0;
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const char *version;
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int i = 0;
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
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error_setg(errp, "addr-size %d is out of range (32 - 64)",
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cpu->cfg.addr_size);
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return;
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}
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qemu_init_vcpu(cs);
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env->pvr.regs[0] = PVR0_USE_EXC_MASK
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| PVR0_USE_ICACHE_MASK
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| PVR0_USE_DCACHE_MASK;
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env->pvr.regs[2] = PVR2_D_OPB_MASK
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| PVR2_D_LMB_MASK
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| PVR2_I_OPB_MASK
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| PVR2_I_LMB_MASK
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| PVR2_FPU_EXC_MASK
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| 0;
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version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
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for (i = 0; mb_cpu_lookup[i].name && version; i++) {
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if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
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version_code = mb_cpu_lookup[i].version_id;
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break;
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}
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}
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if (!version_code) {
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qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
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}
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env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
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(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
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(cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
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(cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
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(cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
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(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
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(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
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(version_code << PVR0_VERSION_SHIFT) |
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(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
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cpu->cfg.pvr_user1;
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env->pvr.regs[1] = cpu->cfg.pvr_user2;
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env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
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(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
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(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
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(cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
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(cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
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(cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
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(cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
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(cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
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(cpu->cfg.dopb_bus_exception ?
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PVR2_DOPB_BUS_EXC_MASK : 0) |
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(cpu->cfg.iopb_bus_exception ?
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PVR2_IOPB_BUS_EXC_MASK : 0) |
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(cpu->cfg.div_zero_exception ?
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PVR2_DIV_ZERO_EXC_MASK : 0) |
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(cpu->cfg.illegal_opcode_exception ?
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PVR2_ILL_OPCODE_EXC_MASK : 0) |
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(cpu->cfg.unaligned_exceptions ?
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PVR2_UNALIGNED_EXC_MASK : 0) |
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(cpu->cfg.opcode_0_illegal ?
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PVR2_OPCODE_0x0_ILL_MASK : 0);
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env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
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PVR5_DCACHE_WRITEBACK_MASK : 0;
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env->pvr.regs[10] = 0x0c000000 | /* Default to spartan 3a dsp family. */
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(cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT;
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env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
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16 << 17;
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mcc->parent_realize(dev, errp);
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}
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static void mb_cpu_initfn(Object *obj)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
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CPUMBState *env = &cpu->env;
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cpu_set_cpustate_pointers(cpu);
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
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#ifndef CONFIG_USER_ONLY
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/* Inbound IRQ and FIR lines */
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qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
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#endif
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}
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static const VMStateDescription vmstate_mb_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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static Property mb_properties[] = {
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DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
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DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
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false),
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/*
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* This is the C_ADDR_SIZE synth-time configuration option of the
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* MicroBlaze cores. Supported values range between 32 and 64.
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*
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* When set to > 32, 32bit MicroBlaze can emit load/stores
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* with extended addressing.
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*/
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DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
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/* If use-fpu > 0 - FPU is enabled
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* If use-fpu = 2 - Floating point conversion and square root instructions
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* are enabled
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*/
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DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
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/* If use-hw-mul > 0 - Multiplier is enabled
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* If use-hw-mul = 2 - 64-bit multiplier is enabled
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*/
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DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
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DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
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DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
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DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
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DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
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DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
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DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
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false),
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DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
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/* Enables bus exceptions on failed data accesses (load/stores). */
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DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
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cfg.dopb_bus_exception, false),
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/* Enables bus exceptions on failed instruction fetches. */
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DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
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cfg.iopb_bus_exception, false),
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DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
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cfg.illegal_opcode_exception, false),
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DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
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cfg.div_zero_exception, false),
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DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
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cfg.unaligned_exceptions, false),
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DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
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cfg.opcode_0_illegal, false),
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DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
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DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
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DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
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DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
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{
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return object_class_by_name(TYPE_MICROBLAZE_CPU);
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}
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static void mb_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
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device_class_set_parent_realize(dc, mb_cpu_realizefn,
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&mcc->parent_realize);
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device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
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cc->class_by_name = mb_cpu_class_by_name;
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cc->has_work = mb_cpu_has_work;
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cc->do_interrupt = mb_cpu_do_interrupt;
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cc->do_unaligned_access = mb_cpu_do_unaligned_access;
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cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
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cc->dump_state = mb_cpu_dump_state;
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cc->set_pc = mb_cpu_set_pc;
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cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
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cc->gdb_read_register = mb_cpu_gdb_read_register;
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cc->gdb_write_register = mb_cpu_gdb_write_register;
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cc->tlb_fill = mb_cpu_tlb_fill;
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#ifndef CONFIG_USER_ONLY
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cc->do_transaction_failed = mb_cpu_transaction_failed;
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cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
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#endif
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dc->vmsd = &vmstate_mb_cpu;
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device_class_set_props(dc, mb_properties);
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cc->gdb_num_core_regs = 32 + 27;
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cc->disas_set_info = mb_disas_set_info;
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cc->tcg_initialize = mb_tcg_init;
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}
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static const TypeInfo mb_cpu_type_info = {
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.name = TYPE_MICROBLAZE_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(MicroBlazeCPU),
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.instance_init = mb_cpu_initfn,
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.class_size = sizeof(MicroBlazeCPUClass),
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.class_init = mb_cpu_class_init,
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};
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static void mb_cpu_register_types(void)
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{
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type_register_static(&mb_cpu_type_info);
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}
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type_init(mb_cpu_register_types)
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