7a9ccb869c
Keep all 32-bit values zero extended in the register, not solely when addresses are 32 bits. This eliminates a dependency on TARGET_LONG_BITS. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
249 lines
8.4 KiB
C
249 lines
8.4 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef I386_TCG_TARGET_H
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#define I386_TCG_TARGET_H
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#define TCG_TARGET_INSN_UNIT_SIZE 1
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 31
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#ifdef __x86_64__
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# define TCG_TARGET_REG_BITS 64
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# define TCG_TARGET_NB_REGS 32
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# define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB)
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#else
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# define TCG_TARGET_REG_BITS 32
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# define TCG_TARGET_NB_REGS 24
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# define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX
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#endif
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typedef enum {
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TCG_REG_EAX = 0,
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TCG_REG_ECX,
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TCG_REG_EDX,
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TCG_REG_EBX,
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TCG_REG_ESP,
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TCG_REG_EBP,
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TCG_REG_ESI,
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TCG_REG_EDI,
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/* 64-bit registers; always define the symbols to avoid
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too much if-deffing. */
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_XMM0,
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TCG_REG_XMM1,
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TCG_REG_XMM2,
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TCG_REG_XMM3,
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TCG_REG_XMM4,
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TCG_REG_XMM5,
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TCG_REG_XMM6,
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TCG_REG_XMM7,
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/* 64-bit registers; likewise always define. */
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TCG_REG_XMM8,
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TCG_REG_XMM9,
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TCG_REG_XMM10,
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TCG_REG_XMM11,
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TCG_REG_XMM12,
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TCG_REG_XMM13,
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TCG_REG_XMM14,
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TCG_REG_XMM15,
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TCG_REG_RAX = TCG_REG_EAX,
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TCG_REG_RCX = TCG_REG_ECX,
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TCG_REG_RDX = TCG_REG_EDX,
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TCG_REG_RBX = TCG_REG_EBX,
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TCG_REG_RSP = TCG_REG_ESP,
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TCG_REG_RBP = TCG_REG_EBP,
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TCG_REG_RSI = TCG_REG_ESI,
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TCG_REG_RDI = TCG_REG_EDI,
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TCG_AREG0 = TCG_REG_EBP,
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TCG_REG_CALL_STACK = TCG_REG_ESP
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} TCGReg;
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/* used for function call generation */
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#define TCG_TARGET_STACK_ALIGN 16
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#if defined(_WIN64)
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#define TCG_TARGET_CALL_STACK_OFFSET 32
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#else
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#endif
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#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
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#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
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#if defined(_WIN64)
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# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF
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# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC
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#elif TCG_TARGET_REG_BITS == 64
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# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
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# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
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#else
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# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
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# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF
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#endif
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extern bool have_bmi1;
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extern bool have_popcnt;
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extern bool have_avx1;
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extern bool have_avx2;
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extern bool have_avx512bw;
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extern bool have_avx512dq;
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extern bool have_avx512vbmi2;
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extern bool have_avx512vl;
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extern bool have_movbe;
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extern bool have_atomic16;
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/* optional instructions */
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#define TCG_TARGET_HAS_div2_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_andc_i32 have_bmi1
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 1
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#define TCG_TARGET_HAS_ctz_i32 1
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#define TCG_TARGET_HAS_ctpop_i32 have_popcnt
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_muls2_i32 1
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#if TCG_TARGET_REG_BITS == 64
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/* Keep 32-bit values zero-extended in a register. */
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#define TCG_TARGET_HAS_extrl_i64_i32 1
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#define TCG_TARGET_HAS_extrh_i64_i32 1
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#define TCG_TARGET_HAS_div2_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_andc_i64 have_bmi1
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_clz_i64 1
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#define TCG_TARGET_HAS_ctz_i64 1
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#define TCG_TARGET_HAS_ctpop_i64 have_popcnt
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 1
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#define TCG_TARGET_HAS_muls2_i64 1
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#define TCG_TARGET_HAS_muluh_i64 0
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#define TCG_TARGET_HAS_mulsh_i64 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#else
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#define TCG_TARGET_HAS_qemu_st8_i32 1
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#endif
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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/* We do not support older SSE systems, only beginning with AVX1. */
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#define TCG_TARGET_HAS_v64 have_avx1
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#define TCG_TARGET_HAS_v128 have_avx1
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#define TCG_TARGET_HAS_v256 have_avx2
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec have_avx512vl
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#define TCG_TARGET_HAS_nand_vec have_avx512vl
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#define TCG_TARGET_HAS_nor_vec have_avx512vl
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#define TCG_TARGET_HAS_eqv_vec have_avx512vl
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#define TCG_TARGET_HAS_not_vec have_avx512vl
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#define TCG_TARGET_HAS_neg_vec 0
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#define TCG_TARGET_HAS_abs_vec 1
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#define TCG_TARGET_HAS_roti_vec have_avx512vl
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#define TCG_TARGET_HAS_rots_vec 0
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#define TCG_TARGET_HAS_rotv_vec have_avx512vl
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 1
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#define TCG_TARGET_HAS_shv_vec have_avx2
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec have_avx512vl
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#define TCG_TARGET_HAS_cmpsel_vec -1
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#define TCG_TARGET_deposit_i32_valid(ofs, len) \
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(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
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((ofs) == 0 && (len) == 16))
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#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
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/* Check for the possibility of high-byte extraction and, for 64-bit,
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zero-extending 32-bit right-shift. */
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#define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8)
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#define TCG_TARGET_extract_i64_valid(ofs, len) \
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(((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
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/* This defines the natural memory order supported by this
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* architecture before guarantees made by various barrier
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* instructions.
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*
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* The x86 has a pretty strong memory ordering which only really
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* allows for some stores to be re-ordered after loads.
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*/
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#include "tcg/tcg-mo.h"
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#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_NEED_POOL_LABELS
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#endif
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