a5b0f6d5c0
The tlb data is stored within the CPU env. Therefore, the initialization has to be done after we clear the environment. Otherwise the tlb will have a valid entry for address 0x0. Signed-off-by: Michael Walle <michael@walle.cc>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* QEMU LatticeMico32 CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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/* CPUClass::reset() */
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static void lm32_cpu_reset(CPUState *s)
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{
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LM32CPU *cpu = LM32_CPU(s);
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
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CPULM32State *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(env, 0);
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}
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lcc->parent_reset(s);
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/* reset cpu state */
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memset(env, 0, offsetof(CPULM32State, breakpoints));
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tlb_flush(env, 1);
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}
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static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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LM32CPU *cpu = LM32_CPU(dev);
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
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cpu_reset(CPU(cpu));
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qemu_init_vcpu(&cpu->env);
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lcc->parent_realize(dev, errp);
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}
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static void lm32_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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LM32CPU *cpu = LM32_CPU(obj);
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CPULM32State *env = &cpu->env;
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static bool tcg_initialized;
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cs->env_ptr = env;
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cpu_exec_init(env);
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env->flags = 0;
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if (tcg_enabled() && !tcg_initialized) {
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tcg_initialized = true;
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lm32_translate_init();
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}
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}
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static void lm32_cpu_class_init(ObjectClass *oc, void *data)
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{
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LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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lcc->parent_realize = dc->realize;
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dc->realize = lm32_cpu_realizefn;
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lcc->parent_reset = cc->reset;
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cc->reset = lm32_cpu_reset;
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cc->do_interrupt = lm32_cpu_do_interrupt;
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cpu_class_set_vmsd(cc, &vmstate_lm32_cpu);
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}
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static const TypeInfo lm32_cpu_type_info = {
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.name = TYPE_LM32_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(LM32CPU),
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.instance_init = lm32_cpu_initfn,
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.abstract = false,
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.class_size = sizeof(LM32CPUClass),
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.class_init = lm32_cpu_class_init,
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};
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static void lm32_cpu_register_types(void)
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{
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type_register_static(&lm32_cpu_type_info);
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}
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type_init(lm32_cpu_register_types)
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