Ben Widawsky 6364adacdf hw/cxl/device: Implement the CAP array (8.2.8.1-2) ... This implements all device MMIO up to the first capability. That includes the CXL Device Capabilities Array Register, as well as all of the CXL Device Capability Header Registers. The latter are filled in as they are implemented in the following patches. Endianness and alignment are managed by softmmu memory core. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-05-13 06:13:36 -04:00
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cxl_component.h
cxl_device.h	hw/cxl/device: Implement the CAP array (8.2.8.1-2)	2022-05-13 06:13:36 -04:00
cxl_pci.h
cxl.h