627a0e90dc
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
870 lines
24 KiB
C
870 lines
24 KiB
C
/*
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* Physical memory management
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*
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* Copyright 2011 Red Hat, Inc. and/or its affiliates
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*
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* Authors:
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* Avi Kivity <avi@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include "memory.h"
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#include "exec-memory.h"
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#include "ioport.h"
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#include <assert.h>
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typedef struct AddrRange AddrRange;
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struct AddrRange {
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uint64_t start;
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uint64_t size;
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};
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static AddrRange addrrange_make(uint64_t start, uint64_t size)
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{
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return (AddrRange) { start, size };
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}
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static bool addrrange_equal(AddrRange r1, AddrRange r2)
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{
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return r1.start == r2.start && r1.size == r2.size;
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}
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static uint64_t addrrange_end(AddrRange r)
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{
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return r.start + r.size;
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}
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static AddrRange addrrange_shift(AddrRange range, int64_t delta)
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{
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range.start += delta;
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return range;
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}
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static bool addrrange_intersects(AddrRange r1, AddrRange r2)
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{
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return (r1.start >= r2.start && r1.start < r2.start + r2.size)
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|| (r2.start >= r1.start && r2.start < r1.start + r1.size);
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}
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static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
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{
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uint64_t start = MAX(r1.start, r2.start);
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/* off-by-one arithmetic to prevent overflow */
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uint64_t end = MIN(addrrange_end(r1) - 1, addrrange_end(r2) - 1);
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return addrrange_make(start, end - start + 1);
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}
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struct CoalescedMemoryRange {
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AddrRange addr;
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QTAILQ_ENTRY(CoalescedMemoryRange) link;
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};
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typedef struct FlatRange FlatRange;
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typedef struct FlatView FlatView;
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/* Range of memory in the global map. Addresses are absolute. */
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struct FlatRange {
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MemoryRegion *mr;
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target_phys_addr_t offset_in_region;
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AddrRange addr;
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uint8_t dirty_log_mask;
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};
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/* Flattened global view of current active memory hierarchy. Kept in sorted
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* order.
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*/
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struct FlatView {
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FlatRange *ranges;
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unsigned nr;
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unsigned nr_allocated;
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};
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typedef struct AddressSpace AddressSpace;
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typedef struct AddressSpaceOps AddressSpaceOps;
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/* A system address space - I/O, memory, etc. */
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struct AddressSpace {
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const AddressSpaceOps *ops;
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MemoryRegion *root;
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FlatView current_map;
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};
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struct AddressSpaceOps {
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void (*range_add)(AddressSpace *as, FlatRange *fr);
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void (*range_del)(AddressSpace *as, FlatRange *fr);
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void (*log_start)(AddressSpace *as, FlatRange *fr);
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void (*log_stop)(AddressSpace *as, FlatRange *fr);
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};
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#define FOR_EACH_FLAT_RANGE(var, view) \
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for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
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static bool flatrange_equal(FlatRange *a, FlatRange *b)
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{
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return a->mr == b->mr
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&& addrrange_equal(a->addr, b->addr)
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&& a->offset_in_region == b->offset_in_region;
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}
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static void flatview_init(FlatView *view)
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{
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view->ranges = NULL;
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view->nr = 0;
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view->nr_allocated = 0;
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}
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/* Insert a range into a given position. Caller is responsible for maintaining
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* sorting order.
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*/
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static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
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{
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if (view->nr == view->nr_allocated) {
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view->nr_allocated = MAX(2 * view->nr, 10);
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view->ranges = qemu_realloc(view->ranges,
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view->nr_allocated * sizeof(*view->ranges));
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}
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memmove(view->ranges + pos + 1, view->ranges + pos,
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(view->nr - pos) * sizeof(FlatRange));
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view->ranges[pos] = *range;
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++view->nr;
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}
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static void flatview_destroy(FlatView *view)
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{
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qemu_free(view->ranges);
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}
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static bool can_merge(FlatRange *r1, FlatRange *r2)
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{
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return addrrange_end(r1->addr) == r2->addr.start
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&& r1->mr == r2->mr
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&& r1->offset_in_region + r1->addr.size == r2->offset_in_region
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&& r1->dirty_log_mask == r2->dirty_log_mask;
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}
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/* Attempt to simplify a view by merging ajacent ranges */
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static void flatview_simplify(FlatView *view)
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{
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unsigned i, j;
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i = 0;
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while (i < view->nr) {
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j = i + 1;
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while (j < view->nr
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&& can_merge(&view->ranges[j-1], &view->ranges[j])) {
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view->ranges[i].addr.size += view->ranges[j].addr.size;
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++j;
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}
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++i;
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memmove(&view->ranges[i], &view->ranges[j],
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(view->nr - j) * sizeof(view->ranges[j]));
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view->nr -= j - i;
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}
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}
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static void memory_region_prepare_ram_addr(MemoryRegion *mr);
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static void as_memory_range_add(AddressSpace *as, FlatRange *fr)
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{
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ram_addr_t phys_offset, region_offset;
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memory_region_prepare_ram_addr(fr->mr);
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phys_offset = fr->mr->ram_addr;
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region_offset = fr->offset_in_region;
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/* cpu_register_physical_memory_log() wants region_offset for
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* mmio, but prefers offseting phys_offset for RAM. Humour it.
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*/
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if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
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phys_offset += region_offset;
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region_offset = 0;
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}
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cpu_register_physical_memory_log(fr->addr.start,
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fr->addr.size,
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phys_offset,
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region_offset,
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fr->dirty_log_mask);
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}
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static void as_memory_range_del(AddressSpace *as, FlatRange *fr)
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{
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cpu_register_physical_memory(fr->addr.start, fr->addr.size,
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IO_MEM_UNASSIGNED);
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}
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static void as_memory_log_start(AddressSpace *as, FlatRange *fr)
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{
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cpu_physical_log_start(fr->addr.start, fr->addr.size);
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}
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static void as_memory_log_stop(AddressSpace *as, FlatRange *fr)
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{
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cpu_physical_log_stop(fr->addr.start, fr->addr.size);
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}
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static const AddressSpaceOps address_space_ops_memory = {
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.range_add = as_memory_range_add,
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.range_del = as_memory_range_del,
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.log_start = as_memory_log_start,
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.log_stop = as_memory_log_stop,
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};
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static AddressSpace address_space_memory = {
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.ops = &address_space_ops_memory,
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};
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static const MemoryRegionPortio *find_portio(MemoryRegion *mr, uint64_t offset,
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unsigned width, bool write)
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{
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const MemoryRegionPortio *mrp;
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for (mrp = mr->ops->old_portio; mrp->size; ++mrp) {
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if (offset >= mrp->offset && offset < mrp->offset + mrp->len
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&& width == mrp->size
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&& (write ? (bool)mrp->write : (bool)mrp->read)) {
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return mrp;
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}
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}
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return NULL;
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}
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static void memory_region_iorange_read(IORange *iorange,
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uint64_t offset,
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unsigned width,
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uint64_t *data)
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{
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MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange);
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if (mr->ops->old_portio) {
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const MemoryRegionPortio *mrp = find_portio(mr, offset, width, false);
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*data = ((uint64_t)1 << (width * 8)) - 1;
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if (mrp) {
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*data = mrp->read(mr->opaque, offset - mrp->offset);
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}
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return;
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}
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*data = mr->ops->read(mr->opaque, offset, width);
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}
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static void memory_region_iorange_write(IORange *iorange,
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uint64_t offset,
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unsigned width,
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uint64_t data)
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{
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MemoryRegion *mr = container_of(iorange, MemoryRegion, iorange);
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if (mr->ops->old_portio) {
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const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true);
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if (mrp) {
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mrp->write(mr->opaque, offset - mrp->offset, data);
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}
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return;
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}
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mr->ops->write(mr->opaque, offset, data, width);
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}
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static const IORangeOps memory_region_iorange_ops = {
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.read = memory_region_iorange_read,
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.write = memory_region_iorange_write,
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};
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static void as_io_range_add(AddressSpace *as, FlatRange *fr)
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{
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iorange_init(&fr->mr->iorange, &memory_region_iorange_ops,
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fr->addr.start,fr->addr.size);
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ioport_register(&fr->mr->iorange);
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}
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static void as_io_range_del(AddressSpace *as, FlatRange *fr)
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{
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isa_unassign_ioport(fr->addr.start, fr->addr.size);
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}
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static const AddressSpaceOps address_space_ops_io = {
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.range_add = as_io_range_add,
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.range_del = as_io_range_del,
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};
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static AddressSpace address_space_io = {
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.ops = &address_space_ops_io,
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};
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/* Render a memory region into the global view. Ranges in @view obscure
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* ranges in @mr.
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*/
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static void render_memory_region(FlatView *view,
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MemoryRegion *mr,
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target_phys_addr_t base,
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AddrRange clip)
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{
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MemoryRegion *subregion;
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unsigned i;
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target_phys_addr_t offset_in_region;
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uint64_t remain;
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uint64_t now;
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FlatRange fr;
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AddrRange tmp;
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base += mr->addr;
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tmp = addrrange_make(base, mr->size);
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if (!addrrange_intersects(tmp, clip)) {
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return;
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}
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clip = addrrange_intersection(tmp, clip);
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if (mr->alias) {
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base -= mr->alias->addr;
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base -= mr->alias_offset;
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render_memory_region(view, mr->alias, base, clip);
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return;
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}
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/* Render subregions in priority order. */
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QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
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render_memory_region(view, subregion, base, clip);
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}
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if (!mr->terminates) {
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return;
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}
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offset_in_region = clip.start - base;
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base = clip.start;
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remain = clip.size;
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/* Render the region itself into any gaps left by the current view. */
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for (i = 0; i < view->nr && remain; ++i) {
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if (base >= addrrange_end(view->ranges[i].addr)) {
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continue;
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}
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if (base < view->ranges[i].addr.start) {
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now = MIN(remain, view->ranges[i].addr.start - base);
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fr.mr = mr;
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fr.offset_in_region = offset_in_region;
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fr.addr = addrrange_make(base, now);
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fr.dirty_log_mask = mr->dirty_log_mask;
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flatview_insert(view, i, &fr);
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++i;
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base += now;
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offset_in_region += now;
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remain -= now;
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}
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if (base == view->ranges[i].addr.start) {
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now = MIN(remain, view->ranges[i].addr.size);
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base += now;
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offset_in_region += now;
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remain -= now;
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}
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}
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if (remain) {
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fr.mr = mr;
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fr.offset_in_region = offset_in_region;
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fr.addr = addrrange_make(base, remain);
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fr.dirty_log_mask = mr->dirty_log_mask;
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flatview_insert(view, i, &fr);
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}
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}
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/* Render a memory topology into a list of disjoint absolute ranges. */
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static FlatView generate_memory_topology(MemoryRegion *mr)
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{
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FlatView view;
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flatview_init(&view);
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render_memory_region(&view, mr, 0, addrrange_make(0, UINT64_MAX));
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flatview_simplify(&view);
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return view;
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}
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static void address_space_update_topology(AddressSpace *as)
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{
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FlatView old_view = as->current_map;
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FlatView new_view = generate_memory_topology(as->root);
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unsigned iold, inew;
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FlatRange *frold, *frnew;
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/* Generate a symmetric difference of the old and new memory maps.
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* Kill ranges in the old map, and instantiate ranges in the new map.
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*/
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iold = inew = 0;
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while (iold < old_view.nr || inew < new_view.nr) {
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if (iold < old_view.nr) {
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frold = &old_view.ranges[iold];
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} else {
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frold = NULL;
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}
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if (inew < new_view.nr) {
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frnew = &new_view.ranges[inew];
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} else {
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frnew = NULL;
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}
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if (frold
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&& (!frnew
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|| frold->addr.start < frnew->addr.start
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|| (frold->addr.start == frnew->addr.start
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&& !flatrange_equal(frold, frnew)))) {
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/* In old, but (not in new, or in new but attributes changed). */
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as->ops->range_del(as, frold);
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++iold;
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} else if (frold && frnew && flatrange_equal(frold, frnew)) {
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/* In both (logging may have changed) */
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if (frold->dirty_log_mask && !frnew->dirty_log_mask) {
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as->ops->log_stop(as, frnew);
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} else if (frnew->dirty_log_mask && !frold->dirty_log_mask) {
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as->ops->log_start(as, frnew);
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}
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++iold;
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++inew;
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} else {
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/* In new */
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as->ops->range_add(as, frnew);
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++inew;
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}
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}
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as->current_map = new_view;
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flatview_destroy(&old_view);
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}
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static void memory_region_update_topology(void)
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{
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if (address_space_memory.root) {
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address_space_update_topology(&address_space_memory);
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}
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if (address_space_io.root) {
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address_space_update_topology(&address_space_io);
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}
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}
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void memory_region_init(MemoryRegion *mr,
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const char *name,
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uint64_t size)
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{
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mr->ops = NULL;
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mr->parent = NULL;
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mr->size = size;
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mr->addr = 0;
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mr->offset = 0;
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mr->terminates = false;
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mr->priority = 0;
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mr->may_overlap = false;
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mr->alias = NULL;
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QTAILQ_INIT(&mr->subregions);
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memset(&mr->subregions_link, 0, sizeof mr->subregions_link);
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QTAILQ_INIT(&mr->coalesced);
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mr->name = qemu_strdup(name);
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mr->dirty_log_mask = 0;
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}
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static bool memory_region_access_valid(MemoryRegion *mr,
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target_phys_addr_t addr,
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unsigned size)
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{
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if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
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return false;
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}
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/* Treat zero as compatibility all valid */
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if (!mr->ops->valid.max_access_size) {
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return true;
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}
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if (size > mr->ops->valid.max_access_size
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|| size < mr->ops->valid.min_access_size) {
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return false;
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}
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return true;
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}
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static uint32_t memory_region_read_thunk_n(void *_mr,
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target_phys_addr_t addr,
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unsigned size)
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{
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MemoryRegion *mr = _mr;
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unsigned access_size, access_size_min, access_size_max;
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uint64_t access_mask;
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uint32_t data = 0, tmp;
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unsigned i;
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if (!memory_region_access_valid(mr, addr, size)) {
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return -1U; /* FIXME: better signalling */
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}
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/* FIXME: support unaligned access */
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access_size_min = mr->ops->impl.min_access_size;
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if (!access_size_min) {
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access_size_min = 1;
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}
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access_size_max = mr->ops->impl.max_access_size;
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if (!access_size_max) {
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access_size_max = 4;
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}
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access_size = MAX(MIN(size, access_size_max), access_size_min);
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access_mask = -1ULL >> (64 - access_size * 8);
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addr += mr->offset;
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for (i = 0; i < size; i += access_size) {
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/* FIXME: big-endian support */
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tmp = mr->ops->read(mr->opaque, addr + i, access_size);
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data |= (tmp & access_mask) << (i * 8);
|
|
}
|
|
|
|
return data;
|
|
}
|
|
|
|
static void memory_region_write_thunk_n(void *_mr,
|
|
target_phys_addr_t addr,
|
|
unsigned size,
|
|
uint64_t data)
|
|
{
|
|
MemoryRegion *mr = _mr;
|
|
unsigned access_size, access_size_min, access_size_max;
|
|
uint64_t access_mask;
|
|
unsigned i;
|
|
|
|
if (!memory_region_access_valid(mr, addr, size)) {
|
|
return; /* FIXME: better signalling */
|
|
}
|
|
|
|
/* FIXME: support unaligned access */
|
|
|
|
access_size_min = mr->ops->impl.min_access_size;
|
|
if (!access_size_min) {
|
|
access_size_min = 1;
|
|
}
|
|
access_size_max = mr->ops->impl.max_access_size;
|
|
if (!access_size_max) {
|
|
access_size_max = 4;
|
|
}
|
|
access_size = MAX(MIN(size, access_size_max), access_size_min);
|
|
access_mask = -1ULL >> (64 - access_size * 8);
|
|
addr += mr->offset;
|
|
for (i = 0; i < size; i += access_size) {
|
|
/* FIXME: big-endian support */
|
|
mr->ops->write(mr->opaque, addr + i, (data >> (i * 8)) & access_mask,
|
|
access_size);
|
|
}
|
|
}
|
|
|
|
static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr)
|
|
{
|
|
return memory_region_read_thunk_n(mr, addr, 1);
|
|
}
|
|
|
|
static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr)
|
|
{
|
|
return memory_region_read_thunk_n(mr, addr, 2);
|
|
}
|
|
|
|
static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr)
|
|
{
|
|
return memory_region_read_thunk_n(mr, addr, 4);
|
|
}
|
|
|
|
static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr,
|
|
uint32_t data)
|
|
{
|
|
memory_region_write_thunk_n(mr, addr, 1, data);
|
|
}
|
|
|
|
static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr,
|
|
uint32_t data)
|
|
{
|
|
memory_region_write_thunk_n(mr, addr, 2, data);
|
|
}
|
|
|
|
static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr,
|
|
uint32_t data)
|
|
{
|
|
memory_region_write_thunk_n(mr, addr, 4, data);
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const memory_region_read_thunk[] = {
|
|
memory_region_read_thunk_b,
|
|
memory_region_read_thunk_w,
|
|
memory_region_read_thunk_l,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const memory_region_write_thunk[] = {
|
|
memory_region_write_thunk_b,
|
|
memory_region_write_thunk_w,
|
|
memory_region_write_thunk_l,
|
|
};
|
|
|
|
static void memory_region_prepare_ram_addr(MemoryRegion *mr)
|
|
{
|
|
if (mr->backend_registered) {
|
|
return;
|
|
}
|
|
|
|
mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk,
|
|
memory_region_write_thunk,
|
|
mr,
|
|
mr->ops->endianness);
|
|
mr->backend_registered = true;
|
|
}
|
|
|
|
void memory_region_init_io(MemoryRegion *mr,
|
|
const MemoryRegionOps *ops,
|
|
void *opaque,
|
|
const char *name,
|
|
uint64_t size)
|
|
{
|
|
memory_region_init(mr, name, size);
|
|
mr->ops = ops;
|
|
mr->opaque = opaque;
|
|
mr->terminates = true;
|
|
mr->backend_registered = false;
|
|
}
|
|
|
|
void memory_region_init_ram(MemoryRegion *mr,
|
|
DeviceState *dev,
|
|
const char *name,
|
|
uint64_t size)
|
|
{
|
|
memory_region_init(mr, name, size);
|
|
mr->terminates = true;
|
|
mr->ram_addr = qemu_ram_alloc(dev, name, size);
|
|
mr->backend_registered = true;
|
|
}
|
|
|
|
void memory_region_init_ram_ptr(MemoryRegion *mr,
|
|
DeviceState *dev,
|
|
const char *name,
|
|
uint64_t size,
|
|
void *ptr)
|
|
{
|
|
memory_region_init(mr, name, size);
|
|
mr->terminates = true;
|
|
mr->ram_addr = qemu_ram_alloc_from_ptr(dev, name, size, ptr);
|
|
mr->backend_registered = true;
|
|
}
|
|
|
|
void memory_region_init_alias(MemoryRegion *mr,
|
|
const char *name,
|
|
MemoryRegion *orig,
|
|
target_phys_addr_t offset,
|
|
uint64_t size)
|
|
{
|
|
memory_region_init(mr, name, size);
|
|
mr->alias = orig;
|
|
mr->alias_offset = offset;
|
|
}
|
|
|
|
void memory_region_destroy(MemoryRegion *mr)
|
|
{
|
|
assert(QTAILQ_EMPTY(&mr->subregions));
|
|
memory_region_clear_coalescing(mr);
|
|
qemu_free((char *)mr->name);
|
|
}
|
|
|
|
uint64_t memory_region_size(MemoryRegion *mr)
|
|
{
|
|
return mr->size;
|
|
}
|
|
|
|
void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset)
|
|
{
|
|
mr->offset = offset;
|
|
}
|
|
|
|
void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
|
|
{
|
|
uint8_t mask = 1 << client;
|
|
|
|
mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
|
|
memory_region_update_topology();
|
|
}
|
|
|
|
bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr,
|
|
unsigned client)
|
|
{
|
|
assert(mr->terminates);
|
|
return cpu_physical_memory_get_dirty(mr->ram_addr + addr, 1 << client);
|
|
}
|
|
|
|
void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr)
|
|
{
|
|
assert(mr->terminates);
|
|
return cpu_physical_memory_set_dirty(mr->ram_addr + addr);
|
|
}
|
|
|
|
void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
|
|
{
|
|
FlatRange *fr;
|
|
|
|
FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) {
|
|
if (fr->mr == mr) {
|
|
cpu_physical_sync_dirty_bitmap(fr->addr.start,
|
|
fr->addr.start + fr->addr.size);
|
|
}
|
|
}
|
|
}
|
|
|
|
void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
|
|
{
|
|
/* FIXME */
|
|
}
|
|
|
|
void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr,
|
|
target_phys_addr_t size, unsigned client)
|
|
{
|
|
assert(mr->terminates);
|
|
cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
|
|
mr->ram_addr + addr + size,
|
|
1 << client);
|
|
}
|
|
|
|
void *memory_region_get_ram_ptr(MemoryRegion *mr)
|
|
{
|
|
if (mr->alias) {
|
|
return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
|
|
}
|
|
|
|
assert(mr->terminates);
|
|
|
|
return qemu_get_ram_ptr(mr->ram_addr);
|
|
}
|
|
|
|
static void memory_region_update_coalesced_range(MemoryRegion *mr)
|
|
{
|
|
FlatRange *fr;
|
|
CoalescedMemoryRange *cmr;
|
|
AddrRange tmp;
|
|
|
|
FOR_EACH_FLAT_RANGE(fr, &address_space_memory.current_map) {
|
|
if (fr->mr == mr) {
|
|
qemu_unregister_coalesced_mmio(fr->addr.start, fr->addr.size);
|
|
QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
|
|
tmp = addrrange_shift(cmr->addr,
|
|
fr->addr.start - fr->offset_in_region);
|
|
if (!addrrange_intersects(tmp, fr->addr)) {
|
|
continue;
|
|
}
|
|
tmp = addrrange_intersection(tmp, fr->addr);
|
|
qemu_register_coalesced_mmio(tmp.start, tmp.size);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void memory_region_set_coalescing(MemoryRegion *mr)
|
|
{
|
|
memory_region_clear_coalescing(mr);
|
|
memory_region_add_coalescing(mr, 0, mr->size);
|
|
}
|
|
|
|
void memory_region_add_coalescing(MemoryRegion *mr,
|
|
target_phys_addr_t offset,
|
|
uint64_t size)
|
|
{
|
|
CoalescedMemoryRange *cmr = qemu_malloc(sizeof(*cmr));
|
|
|
|
cmr->addr = addrrange_make(offset, size);
|
|
QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
|
|
memory_region_update_coalesced_range(mr);
|
|
}
|
|
|
|
void memory_region_clear_coalescing(MemoryRegion *mr)
|
|
{
|
|
CoalescedMemoryRange *cmr;
|
|
|
|
while (!QTAILQ_EMPTY(&mr->coalesced)) {
|
|
cmr = QTAILQ_FIRST(&mr->coalesced);
|
|
QTAILQ_REMOVE(&mr->coalesced, cmr, link);
|
|
qemu_free(cmr);
|
|
}
|
|
memory_region_update_coalesced_range(mr);
|
|
}
|
|
|
|
static void memory_region_add_subregion_common(MemoryRegion *mr,
|
|
target_phys_addr_t offset,
|
|
MemoryRegion *subregion)
|
|
{
|
|
MemoryRegion *other;
|
|
|
|
assert(!subregion->parent);
|
|
subregion->parent = mr;
|
|
subregion->addr = offset;
|
|
QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
|
|
if (subregion->may_overlap || other->may_overlap) {
|
|
continue;
|
|
}
|
|
if (offset >= other->offset + other->size
|
|
|| offset + subregion->size <= other->offset) {
|
|
continue;
|
|
}
|
|
printf("warning: subregion collision %llx/%llx vs %llx/%llx\n",
|
|
(unsigned long long)offset,
|
|
(unsigned long long)subregion->size,
|
|
(unsigned long long)other->offset,
|
|
(unsigned long long)other->size);
|
|
}
|
|
QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
|
|
if (subregion->priority >= other->priority) {
|
|
QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
|
|
goto done;
|
|
}
|
|
}
|
|
QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
|
|
done:
|
|
memory_region_update_topology();
|
|
}
|
|
|
|
|
|
void memory_region_add_subregion(MemoryRegion *mr,
|
|
target_phys_addr_t offset,
|
|
MemoryRegion *subregion)
|
|
{
|
|
subregion->may_overlap = false;
|
|
subregion->priority = 0;
|
|
memory_region_add_subregion_common(mr, offset, subregion);
|
|
}
|
|
|
|
void memory_region_add_subregion_overlap(MemoryRegion *mr,
|
|
target_phys_addr_t offset,
|
|
MemoryRegion *subregion,
|
|
unsigned priority)
|
|
{
|
|
subregion->may_overlap = true;
|
|
subregion->priority = priority;
|
|
memory_region_add_subregion_common(mr, offset, subregion);
|
|
}
|
|
|
|
void memory_region_del_subregion(MemoryRegion *mr,
|
|
MemoryRegion *subregion)
|
|
{
|
|
assert(subregion->parent == mr);
|
|
subregion->parent = NULL;
|
|
QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
|
|
memory_region_update_topology();
|
|
}
|
|
|
|
void set_system_memory_map(MemoryRegion *mr)
|
|
{
|
|
address_space_memory.root = mr;
|
|
memory_region_update_topology();
|
|
}
|
|
|
|
void set_system_io_map(MemoryRegion *mr)
|
|
{
|
|
address_space_io.root = mr;
|
|
memory_region_update_topology();
|
|
}
|