qemu/target/arm
Peter Maydell 62593718d7 target/arm: Split M profile MNegPri mmu index into user and priv
For M profile, we currently have an mmu index MNegPri for
"requested execution priority negative". This fails to
distinguish "requested execution priority negative, privileged"
from "requested execution priority negative, usermode", but
the two can return different results for MPU lookups. Fix this
by splitting MNegPri into MNegPriPriv and MNegPriUser, and
similarly for the Secure equivalent MSNegPri.

This takes us from 6 M profile MMU modes to 8, which means
we need to bump NB_MMU_MODES; this is OK since the point
where we are forced to reduce TLB sizes is 9 MMU modes.

(It would in theory be possible to stick with 6 MMU indexes:
{mpu-disabled,user,privileged} x {secure,nonsecure} since
in the MPU-disabled case the result of an MPU lookup is
always the same for both user and privileged code. However
we would then need to rework the TB flags handling to put
user/priv into the TB flags separately from the mmuidx.
Adding an extra couple of mmu indexes is simpler.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1512153879-5291-5-git-send-email-peter.maydell@linaro.org
2017-12-13 17:59:23 +00:00
..
arch_dump.c hmp: fix "dump-quest-memory" segfault (arm) 2017-09-14 15:52:10 +01:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2017-02-07 18:29:59 +00:00
arm-powerctl.c target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-powerctl.h target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-semi.c
cpu64.c target-arm: Enable EL2 feature bit on A53 and A57 2017-01-20 11:15:10 +00:00
cpu-qom.h
cpu.c disas: Dump insn bytes along with capstone disassembly 2017-11-09 08:46:38 +01:00
cpu.h target/arm: Split M profile MNegPri mmu index into user and priv 2017-12-13 17:59:23 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target/arm: Fix GETPC usage in do_paired_cmpxchg64_l/be 2017-11-15 10:34:33 +01:00
helper-a64.h target/arm: check CF_PARALLEL instead of parallel_cpus 2017-10-24 13:53:41 -07:00
helper.c target/arm: Split M profile MNegPri mmu index into user and priv 2017-12-13 17:59:23 +00:00
helper.h fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
internals.h target/arm: Split M profile MNegPri mmu index into user and priv 2017-12-13 17:59:23 +00:00
iwmmxt_helper.c
kvm32.c target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm64.c target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm_arm.h target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm-consts.h arm: add trailing ; after MISMATCH_CHECK 2017-02-01 03:37:18 +02:00
kvm-stub.c
kvm.c hw/arm/virt: allow pmu instantiation with userspace irqchip 2017-09-04 15:21:54 +01:00
machine.c nvic: Implement Security Attribution Unit registers 2017-10-06 16:46:49 +01:00
Makefile.objs
monitor.c
neon_helper.c
op_addsub.h
op_helper.c fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
psci.c fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
trace-events trace-events: fix code style: print 0x before hex numbers 2017-08-01 12:13:07 +01:00
translate-a64.c arm/translate-a64: mark path as unreachable to eliminate warning 2017-11-13 13:55:24 +00:00
translate.c target/arm: Split M profile MNegPri mmu index into user and priv 2017-12-13 17:59:23 +00:00
translate.h tcg: Initialize cpu_env generically 2017-10-24 13:53:42 -07:00