Kito Cheng 620455350a target/riscv: Fix wrong expanding for c.fswsp ... base register is no rs1 not rs2 for fsw. Signed-off-by: Kito Cheng <kito.cheng@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-03-26 03:17:30 -07:00
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insn_trans	target/riscv: Fix wrong expanding for c.fswsp	2019-03-26 03:17:30 -07:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 05:13:24 -07:00
cpu_helper.c	RISC-V: Update load reservation comment in do_interrupt	2019-03-19 05:14:40 -07:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 05:14:39 -07:00
cpu.c	target/riscv: Remove unused struct	2019-03-19 05:14:40 -07:00
cpu.h	RISC-V: linux-user support for RVE ABI	2019-03-19 05:14:39 -07:00
csr.c	RISC-V: Add support for vectored interrupts	2019-03-19 05:14:39 -07:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	RISC-V: Add hooks to use the gdb xml files.	2019-03-19 05:13:24 -07:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-13 10:40:46 +01:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-13 10:40:50 +01:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-13 10:34:06 +01:00
op_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 05:14:38 -07:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
trace-events	RISC-V: Convert trap debugging to trace events	2019-03-19 05:14:40 -07:00
translate.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-22 00:26:39 -07:00