François Baldassari a859595791 hw/arm_gic: Correctly restore nested irq priority ... Upon activating an interrupt, set the corresponding priority bit in the APR/NSAPR registers without touching the currently set bits. In the event of nested interrupts, the GIC will then have the information it needs to restore the priority of the pre-empted interrupt once the higher priority interrupt finishes execution. Signed-off-by: François Baldassari <francois@pebble.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2015-11-19 12:09:52 +00:00
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allwinner-a10-pic.c
apic_common.c
apic.c
arm_gic_common.c
arm_gic_kvm.c
arm_gic.c	hw/arm_gic: Correctly restore nested irq priority	2015-11-19 12:09:52 +00:00
arm_gicv2m.c
arm_gicv3_common.c
arm_gicv3_kvm.c
armv7m_nvic.c
etraxfs_pic.c
exynos4210_combiner.c
exynos4210_gic.c
gic_internal.h
grlib_irqmp.c
heathrow_pic.c
i8259_common.c
i8259.c
imx_avic.c
ioapic_common.c
ioapic.c
lm32_pic.c
Makefile.objs
omap_intc.c
openpic_kvm.c
openpic.c
pl190.c
puv3_intc.c
realview_gic.c
s390_flic_kvm.c
s390_flic.c
sh_intc.c
slavio_intctl.c
vgic_common.h
xics_kvm.c
xics.c
xilinx_intc.c