Siarhei Volkau 6191a807fb target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions ...

These instructions are all dual 16-bit addition/subtraction in
various combinations. The instructions are grouped in pool13,
see the opcode organization in the file.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-19-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

2023-07-10 23:33:38 +02:00

..

sysemu

target/mips: Rework cp0_timer with clock API

2023-07-10 21:53:03 +02:00

tcg

target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions

2023-07-10 23:33:38 +02:00

cpu-defs.c.inc

target/mips: Add support of two XBurst CPUs

2023-07-10 23:33:38 +02:00

cpu-param.h

target/mips: Remove NB_MMU_MODES define

2023-03-13 06:44:37 -07:00

cpu-qom.h

…

cpu.c

target/mips: Implement Loongson CSR instructions

2023-07-10 23:33:37 +02:00

cpu.h

target/mips: Implement Loongson CSR instructions

2023-07-10 23:33:37 +02:00

fpu_helper.h

…

fpu.c

…

gdbstub.c

…

helper.h

target/mips: Implement Loongson CSR instructions

2023-07-10 23:33:37 +02:00

internal.h

target/mips: Implement Loongson CSR instructions

2023-07-10 23:33:37 +02:00

Kconfig

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kvm_mips.h

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kvm.c

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meson.build

meson: Replace softmmu_ss -> system_ss

2023-06-20 10:01:30 +02:00

mips-defs.h

…

msa.c

…