613fa160e1
It was found that running libquantum on riscv-linux qemu produced an incorrect result. After investigation, FP registers are not saved during context switch due to incorrect mstatus.FS. In current implementation tb->flags merges all non-disabled state to dirty. This means the code in mark_fs_dirty in translate.c that handles initial and clean states is unreachable. This patch fixes it and is successfully tested with: libquantum Thanks to Richard for pointing out the actual bug. v3: remove the redundant condition v2: root cause FS problem Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
344 lines
10 KiB
C
344 lines
10 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include "hw/core/cpu.h"
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat-types.h"
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#define TCG_GUEST_DEFAULT_MO 0
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
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#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
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#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
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#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
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#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
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#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
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#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
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#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
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/* Deprecated */
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#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
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#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
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#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
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#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
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#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
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#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
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#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
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#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
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#if defined(TARGET_RISCV32)
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#define RVXLEN RV32
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#elif defined(TARGET_RISCV64)
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#define RVXLEN RV64
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#endif
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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#define RVI RV('I')
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#define RVE RV('E') /* E and I are mutually exclusive */
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#define RVM RV('M')
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#define RVA RV('A')
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#define RVF RV('F')
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#define RVD RV('D')
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#define RVC RV('C')
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#define RVS RV('S')
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#define RVU RV('U')
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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is currently no bit in misa to indicate whether an MMU exists or not
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so a cpu features bitfield is required, likewise for optional PMP support */
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enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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RISCV_FEATURE_MISA
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};
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#define PRIV_VERSION_1_09_1 0x00010901
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#define PRIV_VERSION_1_10_0 0x00011000
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#define PRIV_VERSION_1_11_0 0x00011100
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#define TRANSLATE_PMP_FAIL 2
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#define TRANSLATE_FAIL 1
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#define TRANSLATE_SUCCESS 0
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#define MMU_USER_IDX 3
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#define MAX_RISCV_PMPS (16)
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typedef struct CPURISCVState CPURISCVState;
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#include "pmp.h"
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struct CPURISCVState {
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target_ulong gpr[32];
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uint64_t fpr[32]; /* assume both F and D extensions */
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target_ulong pc;
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target_ulong load_res;
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target_ulong load_val;
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target_ulong frm;
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target_ulong badaddr;
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target_ulong priv_ver;
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target_ulong misa;
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target_ulong misa_mask;
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uint32_t features;
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#ifdef CONFIG_USER_ONLY
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uint32_t elf_flags;
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#endif
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#ifndef CONFIG_USER_ONLY
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target_ulong priv;
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target_ulong resetvec;
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target_ulong mhartid;
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target_ulong mstatus;
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uint32_t mip;
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uint32_t miclaim;
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target_ulong mie;
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target_ulong mideleg;
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target_ulong sptbr; /* until: priv-1.9.1 */
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target_ulong satp; /* since: priv-1.10.0 */
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target_ulong sbadaddr;
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target_ulong mbadaddr;
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target_ulong medeleg;
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target_ulong stvec;
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target_ulong sepc;
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target_ulong scause;
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target_ulong mtvec;
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target_ulong mepc;
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target_ulong mcause;
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target_ulong mtval; /* since: priv-1.10.0 */
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target_ulong scounteren;
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target_ulong mcounteren;
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target_ulong sscratch;
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target_ulong mscratch;
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/* temporary htif regs */
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uint64_t mfromhost;
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uint64_t mtohost;
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uint64_t timecmp;
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/* physical memory protection */
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pmp_table_t pmp_state;
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/* True if in debugger mode. */
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bool debugger;
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#endif
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float_status fp_status;
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/* Fields from here on are preserved across CPU reset. */
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QEMUTimer *timer; /* Internal timer */
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};
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#define RISCV_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
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#define RISCV_CPU(obj) \
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OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
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#define RISCV_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
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/**
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* RISCVCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A RISCV CPU model.
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*/
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typedef struct RISCVCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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} RISCVCPUClass;
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/**
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* RISCVCPU:
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* @env: #CPURISCVState
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*
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* A RISCV CPU.
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*/
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typedef struct RISCVCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPURISCVState env;
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/* Configuration Settings */
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struct {
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bool ext_i;
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bool ext_e;
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bool ext_g;
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bool ext_m;
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bool ext_a;
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bool ext_f;
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bool ext_d;
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bool ext_c;
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bool ext_s;
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bool ext_u;
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bool ext_counters;
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bool ext_ifencei;
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bool ext_icsr;
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char *priv_spec;
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char *user_spec;
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bool mmu;
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bool pmp;
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} cfg;
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} RISCVCPU;
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static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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{
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return (env->misa & ext) != 0;
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}
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static inline bool riscv_feature(CPURISCVState *env, int feature)
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{
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return env->features & (1ULL << feature);
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}
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#include "cpu_user.h"
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#include "cpu_bits.h"
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extern const char * const riscv_int_regnames[];
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extern const char * const riscv_fpr_regnames[];
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extern const char * const riscv_excp_names[];
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extern const char * const riscv_intr_names[];
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void riscv_cpu_do_interrupt(CPUState *cpu);
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int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
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bool riscv_cpu_fp_enabled(CPURISCVState *env);
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int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr);
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bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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char *riscv_isa_string(RISCVCPU *cpu);
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void riscv_cpu_list(void);
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#define cpu_signal_handler riscv_cpu_signal_handler
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#define cpu_list riscv_cpu_list
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#define cpu_mmu_index riscv_cpu_mmu_index
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#ifndef CONFIG_USER_ONLY
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int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
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uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
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#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
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#endif
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void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
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void riscv_translate_init(void);
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int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
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void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
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uint32_t exception, uintptr_t pc);
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target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
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void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
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#define TB_FLAGS_MMU_MASK 3
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#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
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static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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#ifdef CONFIG_USER_ONLY
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*flags = TB_FLAGS_MSTATUS_FS;
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#else
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*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
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#endif
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}
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int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask);
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int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask);
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static inline void riscv_csr_write(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
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}
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static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
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{
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target_ulong val = 0;
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riscv_csrrw(env, csrno, &val, 0, 0);
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return val;
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}
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typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
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typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
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target_ulong *ret_value);
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typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
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target_ulong new_value);
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typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
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target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
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typedef struct {
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riscv_csr_predicate_fn predicate;
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riscv_csr_read_fn read;
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riscv_csr_write_fn write;
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riscv_csr_op_fn op;
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} riscv_csr_operations;
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void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
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void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
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typedef CPURISCVState CPUArchState;
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typedef RISCVCPU ArchCPU;
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#include "exec/cpu-all.h"
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#endif /* RISCV_CPU_H */
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