627 lines
18 KiB
C
627 lines
18 KiB
C
/*
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* PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "mmu-hash64.h"
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//#define DEBUG_MMU
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//#define DEBUG_SLB
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
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#else
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# define LOG_MMU(...) do { } while (0)
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# define LOG_MMU_STATE(cpu) do { } while (0)
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#endif
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#ifdef DEBUG_SLB
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# define LOG_SLB(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_SLB(...) do { } while (0)
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#endif
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/*
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* Used to indicate whether we have allocated htab in the
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* host kernel
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*/
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bool kvmppc_kern_htab;
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/*
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* SLB handling
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*/
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static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
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{
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uint64_t esid_256M, esid_1T;
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int n;
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LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
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esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
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esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
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for (n = 0; n < env->slb_nr; n++) {
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ppc_slb_t *slb = &env->slb[n];
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LOG_SLB("%s: slot %d %016" PRIx64 " %016"
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PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
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/* We check for 1T matches on all MMUs here - if the MMU
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* doesn't have 1T segment support, we will have prevented 1T
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* entries from being inserted in the slbmte code. */
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if (((slb->esid == esid_256M) &&
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((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
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|| ((slb->esid == esid_1T) &&
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((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
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return slb;
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}
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}
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return NULL;
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}
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void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
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{
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int i;
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uint64_t slbe, slbv;
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cpu_synchronize_state(CPU(ppc_env_get_cpu(env)));
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cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
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for (i = 0; i < env->slb_nr; i++) {
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slbe = env->slb[i].esid;
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slbv = env->slb[i].vsid;
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if (slbe == 0 && slbv == 0) {
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continue;
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}
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cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
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i, slbe, slbv);
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}
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}
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void helper_slbia(CPUPPCState *env)
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{
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int n, do_invalidate;
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do_invalidate = 0;
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/* XXX: Warning: slbia never invalidates the first segment */
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for (n = 1; n < env->slb_nr; n++) {
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ppc_slb_t *slb = &env->slb[n];
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if (slb->esid & SLB_ESID_V) {
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slb->esid &= ~SLB_ESID_V;
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in QEMU, we just invalidate all TLBs
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*/
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do_invalidate = 1;
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}
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}
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if (do_invalidate) {
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tlb_flush(env, 1);
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}
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}
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void helper_slbie(CPUPPCState *env, target_ulong addr)
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{
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ppc_slb_t *slb;
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slb = slb_lookup(env, addr);
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if (!slb) {
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return;
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}
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if (slb->esid & SLB_ESID_V) {
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slb->esid &= ~SLB_ESID_V;
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in QEMU, we just invalidate all TLBs
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*/
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tlb_flush(env, 1);
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}
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}
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int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
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{
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (rb & (0x1000 - env->slb_nr)) {
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return -1; /* Reserved bits set or slot too high */
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}
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if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
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return -1; /* Bad segment size */
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}
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if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
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return -1; /* 1T segment on MMU that doesn't support it */
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}
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/* Mask out the slot number as we store the entry */
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slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
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slb->vsid = rs;
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LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
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" %016" PRIx64 "\n", __func__, slot, rb, rs,
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slb->esid, slb->vsid);
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return 0;
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}
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static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
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target_ulong *rt)
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{
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (slot >= env->slb_nr) {
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return -1;
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}
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*rt = slb->esid;
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return 0;
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}
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static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
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target_ulong *rt)
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{
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (slot >= env->slb_nr) {
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return -1;
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}
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*rt = slb->vsid;
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return 0;
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}
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void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
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{
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if (ppc_store_slb(env, rb, rs) < 0) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL);
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}
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}
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target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
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{
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target_ulong rt = 0;
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if (ppc_load_slb_esid(env, rb, &rt) < 0) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL);
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}
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return rt;
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}
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target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
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{
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target_ulong rt = 0;
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if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL);
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}
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return rt;
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}
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/*
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* 64-bit hash table MMU handling
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*/
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static int ppc_hash64_pte_prot(CPUPPCState *env,
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ppc_slb_t *slb, ppc_hash_pte64_t pte)
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{
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unsigned pp, key;
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/* Some pp bit combinations have undefined behaviour, so default
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* to no access in those cases */
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int prot = 0;
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key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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prot = PAGE_READ | PAGE_WRITE;
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break;
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case 0x3:
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case 0x6:
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prot = PAGE_READ;
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break;
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}
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} else {
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switch (pp) {
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case 0x0:
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case 0x6:
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prot = 0;
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break;
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case 0x1:
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case 0x3:
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prot = PAGE_READ;
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break;
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case 0x2:
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prot = PAGE_READ | PAGE_WRITE;
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break;
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}
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}
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/* No execute if either noexec or guarded bits set */
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if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
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|| (slb->vsid & SLB_VSID_N)) {
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prot |= PAGE_EXEC;
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}
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return prot;
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}
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static int ppc_hash64_amr_prot(CPUPPCState *env, ppc_hash_pte64_t pte)
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{
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int key, amrbits;
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int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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/* Only recent MMUs implement Virtual Page Class Key Protection */
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if (!(env->mmu_model & POWERPC_MMU_AMR)) {
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return prot;
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}
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key = HPTE64_R_KEY(pte.pte1);
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amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
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/* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
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/* env->spr[SPR_AMR]); */
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/*
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* A store is permitted if the AMR bit is 0. Remove write
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* protection if it is set.
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*/
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if (amrbits & 0x2) {
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prot &= ~PAGE_WRITE;
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}
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/*
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* A load is permitted if the AMR bit is 0. Remove read
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* protection if it is set.
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*/
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if (amrbits & 0x1) {
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prot &= ~PAGE_READ;
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}
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return prot;
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}
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uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
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{
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uint64_t token = 0;
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hwaddr pte_offset;
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pte_offset = pte_index * HASH_PTE_SIZE_64;
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if (kvmppc_kern_htab) {
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/*
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* HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
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*/
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token = kvmppc_hash64_read_pteg(cpu, pte_index);
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if (token) {
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return token;
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}
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/*
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* pteg read failed, even though we have allocated htab via
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* kvmppc_reset_htab.
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*/
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return 0;
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}
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/*
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* HTAB is controlled by QEMU. Just point to the internally
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* accessible PTEG.
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*/
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if (cpu->env.external_htab) {
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token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
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} else if (cpu->env.htab_base) {
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token = cpu->env.htab_base + pte_offset;
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}
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return token;
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}
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void ppc_hash64_stop_access(uint64_t token)
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{
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if (kvmppc_kern_htab) {
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return kvmppc_hash64_free_pteg(token);
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}
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}
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static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr hash,
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bool secondary, target_ulong ptem,
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ppc_hash_pte64_t *pte)
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{
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int i;
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uint64_t token;
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target_ulong pte0, pte1;
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target_ulong pte_index;
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pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
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token = ppc_hash64_start_access(ppc_env_get_cpu(env), pte_index);
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if (!token) {
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return -1;
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}
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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pte0 = ppc_hash64_load_hpte0(env, token, i);
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pte1 = ppc_hash64_load_hpte1(env, token, i);
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if ((pte0 & HPTE64_V_VALID)
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&& (secondary == !!(pte0 & HPTE64_V_SECONDARY))
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&& HPTE64_V_COMPARE(pte0, ptem)) {
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pte->pte0 = pte0;
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pte->pte1 = pte1;
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ppc_hash64_stop_access(token);
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return (pte_index + i) * HASH_PTE_SIZE_64;
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}
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}
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ppc_hash64_stop_access(token);
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/*
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* We didn't find a valid entry.
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*/
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return -1;
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}
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static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
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ppc_slb_t *slb, target_ulong eaddr,
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ppc_hash_pte64_t *pte)
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{
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hwaddr pte_offset;
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hwaddr hash;
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uint64_t vsid, epnshift, epnmask, epn, ptem;
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/* Page size according to the SLB, which we use to generate the
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* EPN for hash table lookup.. When we implement more recent MMU
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* extensions this might be different from the actual page size
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* encoded in the PTE */
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epnshift = (slb->vsid & SLB_VSID_L)
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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epnmask = ~((1ULL << epnshift) - 1);
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if (slb->vsid & SLB_VSID_B) {
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/* 1TB segment */
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
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epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
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hash = vsid ^ (vsid << 25) ^ (epn >> epnshift);
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} else {
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/* 256M segment */
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
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epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
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hash = vsid ^ (epn >> epnshift);
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}
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ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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/* Primary PTEG lookup */
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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pte_offset = ppc_hash64_pteg_search(env, hash, 0, ptem, pte);
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if (pte_offset == -1) {
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/* Secondary PTEG lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ptem, ~hash);
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pte_offset = ppc_hash64_pteg_search(env, ~hash, 1, ptem, pte);
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}
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return pte_offset;
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}
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static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
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target_ulong eaddr)
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{
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hwaddr rpn = pte.pte1 & HPTE64_R_RPN;
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/* FIXME: Add support for SLLP extended page sizes */
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int target_page_bits = (slb->vsid & SLB_VSID_L)
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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hwaddr mask = (1ULL << target_page_bits) - 1;
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return (rpn & ~mask) | (eaddr & mask);
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}
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int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
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int rwx, int mmu_idx)
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{
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CPUState *cs = CPU(ppc_env_get_cpu(env));
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ppc_slb_t *slb;
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hwaddr pte_offset;
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ppc_hash_pte64_t pte;
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int pp_prot, amr_prot, prot;
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uint64_t new_pte1;
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const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
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hwaddr raddr;
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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/* 1. Handle real mode accesses */
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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/* Translation is off */
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/* In real mode the top 4 effective address bits are ignored */
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raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
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tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
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TARGET_PAGE_SIZE);
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return 0;
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}
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/* 2. Translation is on, so look up the SLB */
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slb = slb_lookup(env, eaddr);
|
|
|
|
if (!slb) {
|
|
if (rwx == 2) {
|
|
cs->exception_index = POWERPC_EXCP_ISEG;
|
|
env->error_code = 0;
|
|
} else {
|
|
cs->exception_index = POWERPC_EXCP_DSEG;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = eaddr;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/* 3. Check for segment level no-execute violation */
|
|
if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
|
|
cs->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x10000000;
|
|
return 1;
|
|
}
|
|
|
|
/* 4. Locate the PTE in the hash table */
|
|
pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
|
|
if (pte_offset == -1) {
|
|
if (rwx == 2) {
|
|
cs->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x40000000;
|
|
} else {
|
|
cs->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = eaddr;
|
|
if (rwx == 1) {
|
|
env->spr[SPR_DSISR] = 0x42000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x40000000;
|
|
}
|
|
}
|
|
return 1;
|
|
}
|
|
LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
|
|
|
|
/* 5. Check access permissions */
|
|
|
|
pp_prot = ppc_hash64_pte_prot(env, slb, pte);
|
|
amr_prot = ppc_hash64_amr_prot(env, pte);
|
|
prot = pp_prot & amr_prot;
|
|
|
|
if ((need_prot[rwx] & ~prot) != 0) {
|
|
/* Access right violation */
|
|
LOG_MMU("PTE access rejected\n");
|
|
if (rwx == 2) {
|
|
cs->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x08000000;
|
|
} else {
|
|
target_ulong dsisr = 0;
|
|
|
|
cs->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = eaddr;
|
|
if (need_prot[rwx] & ~pp_prot) {
|
|
dsisr |= 0x08000000;
|
|
}
|
|
if (rwx == 1) {
|
|
dsisr |= 0x02000000;
|
|
}
|
|
if (need_prot[rwx] & ~amr_prot) {
|
|
dsisr |= 0x00200000;
|
|
}
|
|
env->spr[SPR_DSISR] = dsisr;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
LOG_MMU("PTE access granted !\n");
|
|
|
|
/* 6. Update PTE referenced and changed bits if necessary */
|
|
|
|
new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
|
|
if (rwx == 1) {
|
|
new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
|
|
} else {
|
|
/* Treat the page as read-only for now, so that a later write
|
|
* will pass through this function again to set the C bit */
|
|
prot &= ~PAGE_WRITE;
|
|
}
|
|
|
|
if (new_pte1 != pte.pte1) {
|
|
ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64,
|
|
pte.pte0, new_pte1);
|
|
}
|
|
|
|
/* 7. Determine the real address from the PTE */
|
|
|
|
raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
|
|
|
|
tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
|
|
prot, mmu_idx, TARGET_PAGE_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
|
|
{
|
|
ppc_slb_t *slb;
|
|
hwaddr pte_offset;
|
|
ppc_hash_pte64_t pte;
|
|
|
|
if (msr_dr == 0) {
|
|
/* In real mode the top 4 effective address bits are ignored */
|
|
return addr & 0x0FFFFFFFFFFFFFFFULL;
|
|
}
|
|
|
|
slb = slb_lookup(env, addr);
|
|
if (!slb) {
|
|
return -1;
|
|
}
|
|
|
|
pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte);
|
|
if (pte_offset == -1) {
|
|
return -1;
|
|
}
|
|
|
|
return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
|
|
}
|
|
|
|
void ppc_hash64_store_hpte(CPUPPCState *env,
|
|
target_ulong pte_index,
|
|
target_ulong pte0, target_ulong pte1)
|
|
{
|
|
CPUState *cs = CPU(ppc_env_get_cpu(env));
|
|
|
|
if (kvmppc_kern_htab) {
|
|
return kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
|
|
}
|
|
|
|
pte_index *= HASH_PTE_SIZE_64;
|
|
if (env->external_htab) {
|
|
stq_p(env->external_htab + pte_index, pte0);
|
|
stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
|
|
} else {
|
|
stq_phys(cs->as, env->htab_base + pte_index, pte0);
|
|
stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
|
|
}
|
|
}
|