mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
qemu/target/riscv
History
Bin Meng 495134b75c hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 
Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19 08:25:27 -07:00
..
insn_trans
target/riscv: Implement checks for hfence
2020-06-19 08:24:07 -07:00
cpu_bits.h
target/riscv: Add the MSTATUS_MPV_ISSET helper macro
2020-02-27 13:46:33 -08:00
cpu_helper.c
target/riscv: Report errors validating 2nd-stage PTEs
2020-06-19 08:24:07 -07:00
cpu_user.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
cpu-param.h
tcg: Split out target/arch/cpu-param.h
2019-06-10 07:03:34 -07:00
cpu.c
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
2020-06-19 08:25:27 -07:00
cpu.h
target/riscv: Add the lowRISC Ibex CPU
2020-06-03 09:11:51 -07:00
csr.c
target/riscv: Drop support for ISA spec version 1.09.1
2020-06-03 09:11:51 -07:00
fpu_helper.c
target/riscv: rationalise softfloat includes
2019-08-19 12:07:13 +01:00
gdbstub.c
gdbstub: extend GByteArray to read register helpers
2020-03-17 17:38:38 +00:00
helper.h
target/riscv: Implement checks for hfence
2020-06-19 08:24:07 -07:00
insn16-32.decode
…
insn16-64.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn16.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn32-64.decode
…
insn32.decode
target/riscv: Move the hfence instructions to the rvh decode
2020-06-19 08:24:07 -07:00
instmap.h
target/riscv: progressively load the instruction during decode
2020-02-25 20:20:23 +00:00
Makefile.objs
riscv: hmp: Add a command to show virtual memory mappings
2019-09-17 08:42:43 -07:00
monitor.c
target/riscv: Drop support for ISA spec version 1.09.1
2020-06-03 09:11:51 -07:00
op_helper.c
target/riscv: Implement checks for hfence
2020-06-19 08:24:07 -07:00
pmp.c
target/riscv: Use a smaller guess size for no-MMU PMP
2020-06-19 08:24:07 -07:00
pmp.h
RISC-V: Check for the effective memory privilege mode during PMP checks
2019-06-23 23:44:41 -07:00
trace-events
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
2019-09-17 08:42:42 -07:00
translate.c
target/riscv: Move the hfence instructions to the rvh decode
2020-06-19 08:24:07 -07:00