aab7a3786f
At the moment the handling of init-svtor and cpuwait initial values is split between armsse.c and iotkit-sysctl.c: the code in armsse.c sets the initial state of the CPU object by setting the init-svtor and start-powered-off properties, but the iotkit-sysctl.c code has its own code setting the reset values of its registers (which are then used when updating the CPU when the guest makes runtime changes). Clean this up by making the armsse.c code set properties on the iotkit-sysctl object to define the initial values of the registers, so they always match the initial CPU state, and update the comments in armsse.c accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* ARM IoTKit system control element
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "system control element" which is part of the
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* Arm IoTKit and documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* Specifically, it implements the "system information block" and
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* "system control register" blocks.
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*
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* QEMU interface:
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* + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
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* system information block of the SSE
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* (used to identify whether to provide SSE-200-only registers)
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* + sysbus MMIO region 0: the system information register bank
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* + sysbus MMIO region 1: the system control register bank
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*/
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#ifndef HW_MISC_IOTKIT_SYSCTL_H
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#define HW_MISC_IOTKIT_SYSCTL_H
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#include "hw/sysbus.h"
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#define TYPE_IOTKIT_SYSCTL "iotkit-sysctl"
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#define IOTKIT_SYSCTL(obj) OBJECT_CHECK(IoTKitSysCtl, (obj), \
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TYPE_IOTKIT_SYSCTL)
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typedef struct IoTKitSysCtl {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t secure_debug;
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uint32_t reset_syndrome;
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uint32_t reset_mask;
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uint32_t gretreg;
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uint32_t initsvtor0;
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uint32_t cpuwait;
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uint32_t wicctrl;
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uint32_t scsecctrl;
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uint32_t fclk_div;
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uint32_t sysclk_div;
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uint32_t clock_force;
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uint32_t initsvtor1;
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uint32_t nmi_enable;
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uint32_t ewctrl;
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uint32_t pdcm_pd_sys_sense;
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uint32_t pdcm_pd_sram0_sense;
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uint32_t pdcm_pd_sram1_sense;
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uint32_t pdcm_pd_sram2_sense;
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uint32_t pdcm_pd_sram3_sense;
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/* Properties */
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uint32_t sys_version;
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uint32_t cpuwait_rst;
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uint32_t initsvtor0_rst;
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uint32_t initsvtor1_rst;
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bool is_sse200;
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} IoTKitSysCtl;
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#endif
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