88d2198c08
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Mechanical transformation using the following comby script:
[pattern-x1]
match='''
static const TypeInfo :[i1~.*_info] = {
:[body]
};
static void :[rt1~.*_register_type.](void)
{
type_register_static(&:[i2~.*_info]);
}
type_init(:[rt2~.*_register_type.])
'''
rewrite='''
static const TypeInfo :[i1][] = {
{
:[body]
},
};
DEFINE_TYPES(:[i1])
'''
rule='where :[i1] == :[i2], :[rt1] == :[rt2]'
[pattern-x2]
match='''
static const TypeInfo :[i1a~.*_info] = {
:[body1]
};
...
static const TypeInfo :[i2a~.*_info] = {
:[body2]
};
static void :[rt1~.*_register_type.](void)
{
type_register_static(&:[i1b~.*_info]);
type_register_static(&:[i2b~.*_info]);
}
type_init(:[rt2~.*_register_type.])
'''
rewrite='''
static const TypeInfo :[i1a][] = {
{
:[body1]
},
{
:[body2]
},
};
DEFINE_TYPES(:[i1a])
'''
rule='''
where
:[i1a] == :[i1b],
:[i2a] == :[i2b],
:[rt1] == :[rt2]
'''
and re-indented manually.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231031080603.86889-2-philmd@linaro.org>
211 lines
6.3 KiB
C
211 lines
6.3 KiB
C
/*
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* Aspeed SD Host Controller
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* Eddie James <eajames@linux.ibm.com>
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*
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* Copyright (C) 2019 IBM Corp
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/sd/aspeed_sdhci.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "trace.h"
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#define ASPEED_SDHCI_INFO 0x00
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#define ASPEED_SDHCI_INFO_SLOT1 (1 << 17)
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#define ASPEED_SDHCI_INFO_SLOT0 (1 << 16)
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#define ASPEED_SDHCI_INFO_RESET (1 << 0)
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#define ASPEED_SDHCI_DEBOUNCE 0x04
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#define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
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#define ASPEED_SDHCI_BUS 0x08
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#define ASPEED_SDHCI_SDIO_140 0x10
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#define ASPEED_SDHCI_SDIO_148 0x18
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#define ASPEED_SDHCI_SDIO_240 0x20
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#define ASPEED_SDHCI_SDIO_248 0x28
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#define ASPEED_SDHCI_WP_POL 0xec
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#define ASPEED_SDHCI_CARD_DET 0xf0
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#define ASPEED_SDHCI_IRQ_STAT 0xfc
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#define TO_REG(addr) ((addr) / sizeof(uint32_t))
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static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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uint32_t val = 0;
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AspeedSDHCIState *sdhci = opaque;
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switch (addr) {
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case ASPEED_SDHCI_SDIO_140:
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val = (uint32_t)sdhci->slots[0].capareg;
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break;
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case ASPEED_SDHCI_SDIO_148:
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val = (uint32_t)sdhci->slots[0].maxcurr;
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break;
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case ASPEED_SDHCI_SDIO_240:
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val = (uint32_t)sdhci->slots[1].capareg;
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break;
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case ASPEED_SDHCI_SDIO_248:
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val = (uint32_t)sdhci->slots[1].maxcurr;
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break;
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default:
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if (addr < ASPEED_SDHCI_REG_SIZE) {
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val = sdhci->regs[TO_REG(addr)];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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}
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}
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trace_aspeed_sdhci_read(addr, size, (uint64_t) val);
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return (uint64_t)val;
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}
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static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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AspeedSDHCIState *sdhci = opaque;
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trace_aspeed_sdhci_write(addr, size, val);
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switch (addr) {
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case ASPEED_SDHCI_INFO:
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/* The RESET bit automatically clears. */
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sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
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break;
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case ASPEED_SDHCI_SDIO_140:
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sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;
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break;
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case ASPEED_SDHCI_SDIO_148:
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sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val;
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break;
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case ASPEED_SDHCI_SDIO_240:
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sdhci->slots[1].capareg = (uint64_t)(uint32_t)val;
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break;
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case ASPEED_SDHCI_SDIO_248:
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sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val;
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break;
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default:
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if (addr < ASPEED_SDHCI_REG_SIZE) {
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sdhci->regs[TO_REG(addr)] = (uint32_t)val;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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}
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}
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}
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static const MemoryRegionOps aspeed_sdhci_ops = {
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.read = aspeed_sdhci_read,
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.write = aspeed_sdhci_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void aspeed_sdhci_set_irq(void *opaque, int n, int level)
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{
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AspeedSDHCIState *sdhci = opaque;
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if (level) {
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sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n);
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qemu_irq_raise(sdhci->irq);
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} else {
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sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n);
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qemu_irq_lower(sdhci->irq);
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}
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}
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static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
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/* Create input irqs for the slots */
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qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
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sdhci, NULL, sdhci->num_slots);
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sysbus_init_irq(sbd, &sdhci->irq);
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memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
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sdhci, TYPE_ASPEED_SDHCI, 0x1000);
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sysbus_init_mmio(sbd, &sdhci->iomem);
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for (int i = 0; i < sdhci->num_slots; ++i) {
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Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
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SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
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if (!object_property_set_int(sdhci_slot, "sd-spec-version", 2, errp)) {
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return;
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}
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if (!object_property_set_uint(sdhci_slot, "capareg",
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ASPEED_SDHCI_CAPABILITIES, errp)) {
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return;
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}
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if (!sysbus_realize(sbd_slot, errp)) {
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return;
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}
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sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i));
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memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100,
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&sdhci->slots[i].iomem);
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}
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}
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static void aspeed_sdhci_reset(DeviceState *dev)
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{
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AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
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memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
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sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0;
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if (sdhci->num_slots == 2) {
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sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1;
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}
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sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;
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}
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static const VMStateDescription vmstate_aspeed_sdhci = {
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.name = TYPE_ASPEED_SDHCI,
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static Property aspeed_sdhci_properties[] = {
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DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(classp);
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dc->realize = aspeed_sdhci_realize;
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dc->reset = aspeed_sdhci_reset;
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dc->vmsd = &vmstate_aspeed_sdhci;
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device_class_set_props(dc, aspeed_sdhci_properties);
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}
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static const TypeInfo aspeed_sdhci_types[] = {
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{
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.name = TYPE_ASPEED_SDHCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSDHCIState),
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.class_init = aspeed_sdhci_class_init,
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},
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};
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DEFINE_TYPES(aspeed_sdhci_types)
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