709bcd7da3
The old implementation replaces two insns, swapping between
b <dest>
nop
and
pcaddu18i tmp, <dest>
jirl zero, tmp, <dest> & 0xffff
There is a race condition in which a thread could be stopped at
the jirl, i.e. with the top of the address loaded, and when
restarted we have re-linked to a different TB, so that the top
half no longer matches the bottom half.
Note that while we never directly re-link to a different TB, we
can link, unlink, and link again all while the stopped thread
remains stopped.
The new implementation replaces only one insn, swapping between
b <dest>
and
pcadd tmp, <jmp_addr>
falling through to load the address from tmp, and branch.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
177 lines
5.7 KiB
C
177 lines
5.7 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
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*
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* Based on tcg/riscv/tcg-target.h
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*
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* Copyright (c) 2018 SiFive, Inc
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef LOONGARCH_TCG_TARGET_H
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#define LOONGARCH_TCG_TARGET_H
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/*
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* Loongson removed the (incomplete) 32-bit support from kernel and toolchain
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* for the initial upstreaming of this architecture, so don't bother and just
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* support the LP64* ABI for now.
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*/
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#if defined(__loongarch64)
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# define TCG_TARGET_REG_BITS 64
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#else
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# error unsupported LoongArch register size
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#endif
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_NB_REGS 32
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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typedef enum {
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TCG_REG_ZERO,
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TCG_REG_RA,
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TCG_REG_TP,
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TCG_REG_SP,
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TCG_REG_A0,
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TCG_REG_A1,
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TCG_REG_A2,
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TCG_REG_A3,
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TCG_REG_A4,
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TCG_REG_A5,
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TCG_REG_A6,
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TCG_REG_A7,
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TCG_REG_T0,
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TCG_REG_T1,
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TCG_REG_T2,
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TCG_REG_T3,
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TCG_REG_T4,
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TCG_REG_T5,
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TCG_REG_T6,
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TCG_REG_T7,
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TCG_REG_T8,
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TCG_REG_RESERVED,
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TCG_REG_S9,
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TCG_REG_S0,
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TCG_REG_S1,
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TCG_REG_S2,
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TCG_REG_S3,
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TCG_REG_S4,
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TCG_REG_S5,
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TCG_REG_S6,
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TCG_REG_S7,
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TCG_REG_S8,
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/* aliases */
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TCG_AREG0 = TCG_REG_S0,
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TCG_REG_TMP0 = TCG_REG_T8,
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TCG_REG_TMP1 = TCG_REG_T7,
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TCG_REG_TMP2 = TCG_REG_T6,
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} TCGReg;
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_SP
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
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#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
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/* optional instructions */
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_div2_i32 0
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_muluh_i32 1
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#define TCG_TARGET_HAS_mulsh_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 0
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 1
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#define TCG_TARGET_HAS_clz_i32 1
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#define TCG_TARGET_HAS_ctz_i32 1
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_brcond2 0
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#define TCG_TARGET_HAS_setcond2 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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/* 64-bit operations */
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_div2_i64 0
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_extrl_i64_i32 1
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#define TCG_TARGET_HAS_extrh_i64_i32 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_neg_i64 0
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 1
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#define TCG_TARGET_HAS_clz_i64 1
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#define TCG_TARGET_HAS_ctz_i64 1
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_add2_i64 0
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#define TCG_TARGET_HAS_sub2_i64 0
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_HAS_MEMORY_BSWAP 0
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#endif /* LOONGARCH_TCG_TARGET_H */
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