Yongbok Kim 5e31fdd59f target/mips: Add CP0 PWBase register ... Add PWBase register (CP0 Register 5, Select 5). The PWBase register contains the Page Table Base virtual address. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>		2018-10-18 20:37:20 +02:00
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alpha
arm	target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write	2018-10-16 17:14:55 +01:00
cris	target/cris/translate: Get rid of qemu_log_separate()	2018-10-16 17:57:23 +02:00
hppa	target/hppa: Raise exception 26 on emulated hardware	2018-10-16 15:32:22 -07:00
i386	target/i386: fix translation for icount mode	2018-10-02 19:09:13 +02:00
lm32
m68k
microblaze
mips	target/mips: Add CP0 PWBase register	2018-10-18 20:37:20 +02:00
moxie
nios2
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	target/ppc/cpu-models: Re-group the 970 CPUs together again	2018-09-25 11:12:25 +10:00
riscv	riscv: remove define cpu_init()	2018-09-05 09:58:38 -07:00
s390x	s390x/kvm: enable AP instruction interpretation for guest	2018-10-12 11:32:18 +02:00
sh4	sh4: fix use_icount with linux-user	2018-08-20 00:11:06 +02:00
sparc
tilegx
tricore
unicore32
xtensa	target/xtensa: extract gen_check_interrupts call	2018-10-01 11:08:36 -07:00