qemu/target
Alvin Chang 5e20b88953 target/riscv: Add functions for common matching conditions of trigger
According to RISC-V Debug specification version 0.13 [1] (also applied
to version 1.0 [2] but it has not been ratified yet), there are several
common matching conditions before firing a trigger, including the
enabled privilege levels of the trigger.

This commit adds trigger_common_match() to prepare the common matching
conditions for the type 2/3/6 triggers. For now, we just implement
trigger_priv_match() to check if the enabled privilege levels of the
trigger match CPU's current privilege level.

Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke
trigger_common_match() to check the privilege levels of the type 2 and
type 6 triggers for the breakpoints.

This commit also changes the behavior of looping the triggers. In
previous implementation, if we have a type 2 trigger and
env->virt_enabled is true, we directly return false to stop the loop.
Now we keep looping all the triggers until we find a matched trigger.

Only the execution bit and the executed PC should be futher checked in
riscv_cpu_debug_check_breakpoint().

[1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
[2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240626132247.2761286-2-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-27 12:23:33 +10:00
..
alpha accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
arm gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
avr target/avr: Use translator_lduw 2024-05-15 08:55:19 +02:00
cris target/cris: Use cris_fetch in translate_v10.c.inc 2024-05-15 08:55:19 +02:00
hexagon target/hexagon: idef-parser simplify predicate init 2024-06-08 17:49:36 -07:00
hppa target/hppa: 2024-05-15 11:46:58 +02:00
i386 gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
loongarch target/loongarch: fix a wrong print in cpu dump 2024-06-06 11:58:06 +08:00
m68k accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
microblaze target/microblaze: Use translator_ldl 2024-05-15 08:55:19 +02:00
mips target/mips: Remove unused 'hw/misc/mips_itu.h' header 2024-06-04 10:02:39 +02:00
openrisc accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
ppc gdbstub: move enums into separate header 2024-06-24 10:14:17 +01:00
riscv target/riscv: Add functions for common matching conditions of trigger 2024-06-27 12:23:33 +10:00
rx target/rx: Use translator_ld* 2024-05-15 08:55:19 +02:00
s390x maintainer updates (plugins, gdbstub): 2024-06-24 13:51:11 -07:00
sh4 accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
sparc target/sparc: use signed denominator in sdiv helper 2024-06-19 13:50:22 -07:00
tricore accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
xtensa target/xtensa: Use translator_ldub in xtensa_insn_len 2024-05-15 08:55:19 +02:00
Kconfig meson: make target endianneess available to Kconfig 2024-05-03 15:47:47 +02:00
meson.build exec: Expose 'target_page.h' API to user emulation 2024-04-26 15:28:11 +02:00