5d1270caac
Add trans_* and helper function for Zfbfmin instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230615063302.102409-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
54 lines
1.5 KiB
C++
54 lines
1.5 KiB
C++
/*
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* RISC-V translation routines for the BF16 Standard Extensions.
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*
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* Copyright (c) 2020-2023 PLCT Lab
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ZFBFMIN(ctx) do { \
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if (!ctx->cfg_ptr->ext_zfbfmin) { \
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return false; \
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} \
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} while (0)
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static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZFBFMIN(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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gen_set_rm(ctx, a->rm);
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gen_helper_fcvt_bf16_s(dest, cpu_env, src1);
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gen_set_fpr_hs(ctx, a->rd, dest);
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZFBFMIN(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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gen_set_rm(ctx, a->rm);
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gen_helper_fcvt_s_bf16(dest, cpu_env, src1);
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gen_set_fpr_hs(ctx, a->rd, dest);
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mark_fs_dirty(ctx);
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return true;
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}
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