Alvin Chang a8c0d82f7b disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14 ... Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230907084500.328-1-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> (cherry picked from commit cffa995490) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2023-10-13 18:20:59 +03:00
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alpha.c
capstone.c
cris.c
disas-internal.h	disas: Move softmmu specific code to separate file	2023-05-11 09:49:55 +01:00
disas-mon.c	disas: Move softmmu specific code to separate file	2023-05-11 09:49:55 +01:00
disas.c	disas: Move disas.c into the target-independent source set	2023-05-11 09:51:07 +01:00
hexagon.c
hppa.c
m68k.c
meson.build	disas/riscv: Add support for XThead* instructions	2023-07-10 22:29:14 +10:00
microblaze.c
mips.c
nanomips.c
nios2.c
riscv-xthead.c	disas/riscv: Add support for XThead* instructions	2023-07-10 22:29:14 +10:00
riscv-xthead.h	disas/riscv: Add support for XThead* instructions	2023-07-10 22:29:14 +10:00
riscv-xventana.c	disas/riscv: Add support for XVentanaCondOps	2023-07-10 22:29:14 +10:00
riscv-xventana.h	disas/riscv: Add support for XVentanaCondOps	2023-07-10 22:29:14 +10:00
riscv.c	disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14	2023-10-13 18:20:59 +03:00
riscv.h	riscv/disas: Fix disas output of upper immediates	2023-07-19 14:30:04 +10:00
sh4.c
sparc.c
xtensa.c