24beb03e46
In the case of supporting PMP feature, add PMP state description to vmstate_riscv_cpu. 'vmstate_pmp_addr' and 'num_rules' could be regenerated by pmp_update_rule(). But there exists the problem of updating num_rules repeatedly in pmp_update_rule(). So here extracts pmp_update_rule_addr() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-4-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
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* QEMU RISC-V PMP (Physical Memory Protection)
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*
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* Author: Daire McNamara, daire.mcnamara@emdalo.com
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* Ivan Griffin, ivan.griffin@emdalo.com
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*
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* This provides a RISC-V Physical Memory Protection interface
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_PMP_H
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#define RISCV_PMP_H
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typedef enum {
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PMP_READ = 1 << 0,
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PMP_WRITE = 1 << 1,
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PMP_EXEC = 1 << 2,
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PMP_LOCK = 1 << 7
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} pmp_priv_t;
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typedef enum {
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PMP_AMATCH_OFF, /* Null (off) */
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PMP_AMATCH_TOR, /* Top of Range */
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PMP_AMATCH_NA4, /* Naturally aligned four-byte region */
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PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
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} pmp_am_t;
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typedef struct {
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target_ulong addr_reg;
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uint8_t cfg_reg;
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} pmp_entry_t;
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typedef struct {
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target_ulong sa;
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target_ulong ea;
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} pmp_addr_t;
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typedef struct {
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pmp_entry_t pmp[MAX_RISCV_PMPS];
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pmp_addr_t addr[MAX_RISCV_PMPS];
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uint32_t num_rules;
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} pmp_table_t;
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void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
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target_ulong val);
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target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
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void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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target_ulong val);
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target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
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bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
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target_ulong size, pmp_priv_t priv, target_ulong mode);
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bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
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target_ulong *tlb_size);
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void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
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void pmp_update_rule_nums(CPURISCVState *env);
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#endif
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