2c992b88cc
A64's sd register was similar to H3, and it introduced a new register named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of mmc2 is only 8K and the other mmc controllers has 64K. Also fix allwinner-r40's mmc controller type. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
147 lines
4.4 KiB
C
147 lines
4.4 KiB
C
/*
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* Allwinner (sun4i and above) SD Host Controller emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SD_ALLWINNER_SDHOST_H
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#define HW_SD_ALLWINNER_SDHOST_H
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#include "qom/object.h"
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#include "hw/sysbus.h"
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#include "hw/sd/sd.h"
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/**
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* Object model types
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* @{
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*/
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/** Generic Allwinner SD Host Controller (abstract) */
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#define TYPE_AW_SDHOST "allwinner-sdhost"
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/** Allwinner sun4i family (A10, A12) */
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#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
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/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
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#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
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/** Allwinner sun50i-a64 */
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#define TYPE_AW_SDHOST_SUN50I_A64 TYPE_AW_SDHOST "-sun50i-a64"
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/** Allwinner sun50i-a64 emmc */
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#define TYPE_AW_SDHOST_SUN50I_A64_EMMC TYPE_AW_SDHOST "-sun50i-a64-emmc"
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/** @} */
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/**
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* Object model macros
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* @{
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*/
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OBJECT_DECLARE_TYPE(AwSdHostState, AwSdHostClass, AW_SDHOST)
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/** @} */
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/**
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* Allwinner SD Host Controller object instance state.
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*/
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struct AwSdHostState {
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/*< private >*/
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SysBusDevice busdev;
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/*< public >*/
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/** Secure Digital (SD) bus, which connects to SD card (if present) */
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SDBus sdbus;
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/** Maps I/O registers in physical memory */
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MemoryRegion iomem;
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/** Interrupt output signal to notify CPU */
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qemu_irq irq;
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/** Memory region where DMA transfers are done */
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MemoryRegion *dma_mr;
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/** Address space used internally for DMA transfers */
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AddressSpace dma_as;
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/** Number of bytes left in current DMA transfer */
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uint32_t transfer_cnt;
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/**
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* @name Hardware Registers
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* @{
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*/
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uint32_t global_ctl; /**< Global Control */
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uint32_t clock_ctl; /**< Clock Control */
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uint32_t timeout; /**< Timeout */
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uint32_t bus_width; /**< Bus Width */
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uint32_t block_size; /**< Block Size */
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uint32_t byte_count; /**< Byte Count */
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uint32_t command; /**< Command */
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uint32_t command_arg; /**< Command Argument */
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uint32_t response[4]; /**< Command Response */
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uint32_t irq_mask; /**< Interrupt Mask */
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uint32_t irq_status; /**< Raw Interrupt Status */
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uint32_t status; /**< Status */
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uint32_t fifo_wlevel; /**< FIFO Water Level */
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uint32_t fifo_func_sel; /**< FIFO Function Select */
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uint32_t debug_enable; /**< Debug Enable */
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uint32_t auto12_arg; /**< Auto Command 12 Argument */
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uint32_t newtiming_set; /**< SD New Timing Set */
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uint32_t newtiming_debug; /**< SD New Timing Debug */
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uint32_t hardware_rst; /**< Hardware Reset */
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uint32_t dmac; /**< Internal DMA Controller Control */
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uint32_t desc_base; /**< Descriptor List Base Address */
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uint32_t dmac_status; /**< Internal DMA Controller Status */
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uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
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uint32_t card_threshold; /**< Card Threshold Control */
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uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */
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uint32_t response_crc; /**< Response CRC */
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uint32_t data_crc[8]; /**< Data CRC */
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uint32_t sample_delay; /**< Sample delay control */
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uint32_t status_crc; /**< Status CRC */
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/** @} */
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};
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/**
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* Allwinner SD Host Controller class-level struct.
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*
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* This struct is filled by each sunxi device specific code
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* such that the generic code can use this struct to support
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* all devices.
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*/
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struct AwSdHostClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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/** Maximum buffer size in bytes per DMA descriptor */
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size_t max_desc_size;
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bool is_sun4i;
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/** does the IP block support autocalibration? */
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bool can_calibrate;
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};
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#endif /* HW_SD_ALLWINNER_SDHOST_H */
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