3b5ea01e98
Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread" modes. In per-core mode, some SPRs and IPI doorbells are shared between threads in a core. In per-thread mode, supervisor and user state is not shared between threads. OpenPOWER systems after POWER8 use LPAR per thread mode, and it is required for KVM. Enterprise systems use LPAR per core mode, as they partition the machine by core. Implement a lpar-per-core machine option for powernv machines. This is fixed true for POWER8 machines, and defaults off for P9 and P10. With this change, powernv8 SMT now works sufficiently to run Linux, with a single socket. Multi-threaded KVM guests still have problems, as does multi-socket Linux boot. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
/*
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* QEMU PowerPC PowerNV CPU Core model
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public License
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* as published by the Free Software Foundation; either version 2.1 of
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* the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_CORE_H
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#define PPC_PNV_CORE_H
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#include "hw/cpu/core.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/pnv.h"
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#include "qom/object.h"
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/* Per-core ChipTOD / TimeBase state */
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typedef struct PnvCoreTODState {
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/*
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* POWER10 DD2.0 - big core TFMR drives the state machine on the even
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* small core. Skiboot has a workaround that targets the even small core
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* for CHIPTOD_TO_TB ops.
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*/
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bool big_core_quirk;
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int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
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int tod_sent_to_tb; /* chiptod sent TOD to the core TB */
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/*
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* "Timers" for async TBST events are simulated by mfTFAC because TFAC
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* is polled for such events. These are just used to ensure firmware
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* performs the polling at least a few times.
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*/
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int tb_state_timer;
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int tb_sync_pulse_timer;
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} PnvCoreTODState;
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#define TYPE_PNV_CORE "powernv-cpu-core"
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OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
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PNV_CORE)
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struct PnvCore {
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/*< private >*/
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CPUCore parent_obj;
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/*< public >*/
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PowerPCCPU **threads;
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bool big_core;
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bool lpar_per_core;
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uint32_t pir;
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uint32_t hwid;
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uint64_t hrmor;
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target_ulong scratch[8]; /* SPRC/SPRD indirect SCRATCH registers */
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PnvCoreTODState tod_state;
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PnvChip *chip;
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MemoryRegion xscom_regs;
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};
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struct PnvCoreClass {
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DeviceClass parent_class;
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const MemoryRegionOps *xscom_ops;
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uint64_t xscom_size;
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};
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#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
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#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
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typedef struct PnvCPUState {
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PnvCore *pnv_core;
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Object *intc;
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} PnvCPUState;
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static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
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{
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return (PnvCPUState *)cpu->machine_data;
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}
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struct PnvQuadClass {
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DeviceClass parent_class;
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const MemoryRegionOps *xscom_ops;
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uint64_t xscom_size;
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const MemoryRegionOps *xscom_qme_ops;
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uint64_t xscom_qme_size;
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};
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#define TYPE_PNV_QUAD "powernv-cpu-quad"
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#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
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#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
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OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
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struct PnvQuad {
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DeviceState parent_obj;
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bool special_wakeup_done;
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bool special_wakeup[4];
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uint32_t quad_id;
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MemoryRegion xscom_regs;
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MemoryRegion xscom_qme_regs;
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};
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#endif /* PPC_PNV_CORE_H */
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