53b3169269
The size of SDHCI capabilities register is 64bits, so introduces new Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244). Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [ clg: Fixed code alignment ] Signed-off-by: Cédric Le Goater <clg@redhat.com> |
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allwinner-sdhost.c | ||
aspeed_sdhci.c | ||
bcm2835_sdhost.c | ||
cadence_sdhci.c | ||
core.c | ||
Kconfig | ||
meson.build | ||
npcm7xx_sdhci.c | ||
omap_mmc.c | ||
pl181.c | ||
sd.c | ||
sdhci-internal.h | ||
sdhci-pci.c | ||
sdhci.c | ||
sdmmc-internal.h | ||
ssi-sd.c | ||
trace-events | ||
trace.h |