qemu/lm32 at 5a853fc57a0860da4a55d1448a77845f97e7a9be - qemu

History

Richard Henderson e8b5fae516 cpu: Remove CPU_COMMON This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2019-06-10 07:03:42 -07:00
..
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu-qom.h
cpu.c	cpu: Introduce cpu_set_cpustate_pointers	2019-06-10 07:03:42 -07:00
cpu.h	cpu: Remove CPU_COMMON	2019-06-10 07:03:42 -07:00
gdbstub.c
helper.c	target/lm32: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
helper.h
lm32-semi.c
machine.c
Makefile.objs
op_helper.c	target/lm32: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
README
TODO
translate.c	target/lm32: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00

README

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Semihosting
-----------
Semihosting on this target is supported. Some system calls like read, write
and exit are executed on the host if semihosting is enabled. See
target/lm32-semi.c for all supported system calls. Emulation aware programs
can use this mechanism to shut down the virtual machine and print to the
host console. See the tcg tests for an example.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);