5a7ce25d0d
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-8-philmd@linaro.org>
293 lines
8.9 KiB
PHP
293 lines
8.9 KiB
PHP
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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static bool gen_rrr(DisasContext *ctx, arg_rrr *a,
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DisasExtend src1_ext, DisasExtend src2_ext,
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DisasExtend dst_ext, void (*func)(TCGv, TCGv, TCGv))
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{
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TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
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TCGv src1 = gpr_src(ctx, a->rj, src1_ext);
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TCGv src2 = gpr_src(ctx, a->rk, src2_ext);
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func(dest, src1, src2);
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gen_set_gpr(a->rd, dest, dst_ext);
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return true;
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}
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static bool gen_rri_v(DisasContext *ctx, arg_rr_i *a,
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DisasExtend src_ext, DisasExtend dst_ext,
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void (*func)(TCGv, TCGv, TCGv))
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{
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TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
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TCGv src1 = gpr_src(ctx, a->rj, src_ext);
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TCGv src2 = tcg_constant_tl(a->imm);
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func(dest, src1, src2);
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gen_set_gpr(a->rd, dest, dst_ext);
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return true;
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}
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static bool gen_rri_c(DisasContext *ctx, arg_rr_i *a,
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DisasExtend src_ext, DisasExtend dst_ext,
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void (*func)(TCGv, TCGv, target_long))
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{
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TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
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TCGv src1 = gpr_src(ctx, a->rj, src_ext);
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func(dest, src1, a->imm);
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gen_set_gpr(a->rd, dest, dst_ext);
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return true;
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}
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static bool gen_rrr_sa(DisasContext *ctx, arg_rrr_sa *a,
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DisasExtend src_ext, DisasExtend dst_ext,
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void (*func)(TCGv, TCGv, TCGv, target_long))
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{
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TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
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TCGv src1 = gpr_src(ctx, a->rj, src_ext);
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TCGv src2 = gpr_src(ctx, a->rk, src_ext);
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func(dest, src1, src2, a->sa);
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gen_set_gpr(a->rd, dest, dst_ext);
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return true;
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}
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static bool trans_lu12i_w(DisasContext *ctx, arg_lu12i_w *a)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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tcg_gen_movi_tl(dest, a->imm << 12);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool gen_pc(DisasContext *ctx, arg_r_i *a,
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target_ulong (*func)(target_ulong, int))
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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target_ulong addr = make_address_pc(ctx, func(ctx->base.pc_next, a->imm));
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tcg_gen_movi_tl(dest, addr);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static void gen_slt(TCGv dest, TCGv src1, TCGv src2)
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{
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tcg_gen_setcond_tl(TCG_COND_LT, dest, src1, src2);
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}
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static void gen_sltu(TCGv dest, TCGv src1, TCGv src2)
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{
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tcg_gen_setcond_tl(TCG_COND_LTU, dest, src1, src2);
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}
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static void gen_mulh_w(TCGv dest, TCGv src1, TCGv src2)
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{
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tcg_gen_mul_i64(dest, src1, src2);
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tcg_gen_sari_i64(dest, dest, 32);
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}
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static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv discard = tcg_temp_new();
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tcg_gen_muls2_tl(discard, dest, src1, src2);
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}
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static void gen_mulh_du(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv discard = tcg_temp_new();
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tcg_gen_mulu2_tl(discard, dest, src1, src2);
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}
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static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv zero = tcg_constant_tl(0);
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/*
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* If min / -1, set the divisor to 1.
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* This avoids potential host overflow trap and produces min.
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* If x / 0, set the divisor to 1.
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* This avoids potential host overflow trap;
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* the required result is undefined.
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*/
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tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, INT64_MIN);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t0, src2, -1);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src2, 0);
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tcg_gen_and_tl(ret, ret, t0);
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tcg_gen_or_tl(ret, ret, t1);
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tcg_gen_movcond_tl(TCG_COND_NE, ret, ret, zero, ret, src2);
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}
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static void prep_divisor_du(TCGv ret, TCGv src2)
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{
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TCGv zero = tcg_constant_tl(0);
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TCGv one = tcg_constant_tl(1);
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/*
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* If x / 0, set the divisor to 1.
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* This avoids potential host overflow trap;
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* the required result is undefined.
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, ret, src2, zero, one, src2);
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}
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static void gen_div_d(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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prep_divisor_d(t0, src1, src2);
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tcg_gen_div_tl(dest, src1, t0);
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}
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static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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prep_divisor_d(t0, src1, src2);
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tcg_gen_rem_tl(dest, src1, t0);
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}
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static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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prep_divisor_du(t0, src2);
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tcg_gen_divu_tl(dest, src1, t0);
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}
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static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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prep_divisor_du(t0, src2);
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tcg_gen_remu_tl(dest, src1, t0);
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}
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static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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/* We need not check for integer overflow for div_w. */
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prep_divisor_du(t0, src2);
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tcg_gen_div_tl(dest, src1, t0);
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}
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static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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/* We need not check for integer overflow for rem_w. */
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prep_divisor_du(t0, src2);
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tcg_gen_rem_tl(dest, src1, t0);
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}
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static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_shli_tl(t0, src1, sa);
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tcg_gen_add_tl(dest, t0, src2);
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}
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static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv src2 = tcg_constant_tl(a->imm);
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tcg_gen_deposit_tl(dest, src1, src2, 32, 32);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool trans_lu52i_d(DisasContext *ctx, arg_lu52i_d *a)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = tcg_constant_tl(a->imm);
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tcg_gen_deposit_tl(dest, src1, src2, 52, 12);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static target_ulong gen_pcaddi(target_ulong pc, int imm)
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{
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return pc + (imm << 2);
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}
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static target_ulong gen_pcalau12i(target_ulong pc, int imm)
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{
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return (pc + (imm << 12)) & ~0xfff;
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}
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static target_ulong gen_pcaddu12i(target_ulong pc, int imm)
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{
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return pc + (imm << 12);
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}
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static target_ulong gen_pcaddu18i(target_ulong pc, int imm)
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{
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return pc + ((target_ulong)(imm) << 18);
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}
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static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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tcg_gen_addi_tl(dest, src1, a->imm << 16);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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TRANS(add_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)
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TRANS(add_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
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TRANS(sub_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)
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TRANS(sub_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
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TRANS(and, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)
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TRANS(or, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)
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TRANS(xor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)
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TRANS(nor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_nor_tl)
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TRANS(andn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_andc_tl)
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TRANS(orn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)
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TRANS(slt, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)
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TRANS(sltu, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
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TRANS(mul_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)
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TRANS(mul_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
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TRANS(mulh_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)
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TRANS(mulh_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)
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TRANS(mulh_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
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TRANS(mulh_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
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TRANS(mulw_d_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
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TRANS(mulw_d_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
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TRANS(div_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w)
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TRANS(mod_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w)
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TRANS(div_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du)
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TRANS(mod_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du)
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TRANS(div_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
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TRANS(mod_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
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TRANS(div_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
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TRANS(mod_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
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TRANS(slti, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt)
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TRANS(sltui, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu)
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TRANS(addi_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl)
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TRANS(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
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TRANS(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
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TRANS(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
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TRANS(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
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TRANS(pcaddi, gen_pc, gen_pcaddi)
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TRANS(pcalau12i, gen_pc, gen_pcalau12i)
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TRANS(pcaddu12i, gen_pc, gen_pcaddu12i)
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TRANS(pcaddu18i, gen_pc, gen_pcaddu18i)
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TRANS(andi, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
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TRANS(ori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
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TRANS(xori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl)
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