59c9177338
Implement the MVE VABS functions (both integer and floating point). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-8-peter.maydell@linaro.org
83 lines
3.5 KiB
Plaintext
83 lines
3.5 KiB
Plaintext
# M-profile MVE instruction descriptions
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#
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# Copyright (c) 2021 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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%qd 22:1 13:3
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%qm 5:1 1:3
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&vldr_vstr rn qd imm p a w size l u
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&1op qd qm size
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@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
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# Note that both Rn and Qd are 3 bits only (no D bit)
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@vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr
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@1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm
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@1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0
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# Vector loads and stores
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# Widening loads and narrowing stores:
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# for these P=0 W=0 is 'related encoding'; sz=11 is 'related encoding'
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# This means we need to expand out to multiple patterns for P, W, SZ.
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# For stores the U bit must be 0 but we catch that in the trans_ function.
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# The naming scheme here is "VLDSTB_H == in-memory byte load/store to/from
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# signed halfword element in register", etc.
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VLDSTB_H 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 01 ....... @vldst_wn \
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p=0 w=1 size=1
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VLDSTB_H 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 01 ....... @vldst_wn \
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p=1 size=1
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VLDSTB_W 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 10 ....... @vldst_wn \
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p=0 w=1 size=2
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VLDSTB_W 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 10 ....... @vldst_wn \
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p=1 size=2
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VLDSTH_W 111 . 110 0 a:1 0 1 . 1 ... ... 0 111 10 ....... @vldst_wn \
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p=0 w=1 size=2
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VLDSTH_W 111 . 110 1 a:1 0 w:1 . 1 ... ... 0 111 10 ....... @vldst_wn \
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p=1 size=2
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# Non-widening loads/stores (P=0 W=0 is 'related encoding')
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VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vstr \
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size=0 p=0 w=1
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VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111101 ....... @vldr_vstr \
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size=1 p=0 w=1
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VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111110 ....... @vldr_vstr \
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size=2 p=0 w=1
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111100 ....... @vldr_vstr \
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size=0 p=1
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \
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size=1 p=1
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \
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size=2 p=1
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# Vector miscellaneous
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VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
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VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op
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VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op
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VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op
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VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op
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VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz
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VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op
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VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op
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