5861a33898
The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical, just that the MPIC one can also raise critical interrupts. Combine those two and check for critical raise capability during runtime. Signed-off-by: Alexander Graf <agraf@suse.de>
22 lines
814 B
C
22 lines
814 B
C
#if !defined(__OPENPIC_H__)
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#define __OPENPIC_H__
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/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
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enum {
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OPENPIC_OUTPUT_INT = 0, /* IRQ */
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OPENPIC_OUTPUT_CINT, /* critical IRQ */
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OPENPIC_OUTPUT_MCK, /* Machine check event */
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OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
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OPENPIC_OUTPUT_RESET, /* Core reset event */
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OPENPIC_OUTPUT_NB,
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};
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/* OpenPIC capability flags */
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#define OPENPIC_FLAG_IDE_CRIT (1 << 0)
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qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
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qemu_irq **irqs, qemu_irq irq_out);
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qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
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int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
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#endif /* __OPENPIC_H__ */
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