57a3a62265
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
55 lines
1.7 KiB
C
55 lines
1.7 KiB
C
/*
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* QEMU lowRISC Ibex Timer device
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*
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* Copyright (c) 2021 Western Digital
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_IBEX_TIMER_H
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#define HW_IBEX_TIMER_H
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#include "hw/sysbus.h"
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#define TYPE_IBEX_TIMER "ibex-timer"
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OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
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struct IbexTimerState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint32_t timer_ctrl;
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uint32_t timer_cfg0;
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uint32_t timer_compare_lower0;
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uint32_t timer_compare_upper0;
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uint32_t timer_intr_enable;
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uint32_t timer_intr_state;
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uint32_t timer_intr_test;
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uint32_t timebase_freq;
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qemu_irq irq;
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qemu_irq m_timer_irq;
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};
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#endif /* HW_IBEX_TIMER_H */
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